Patchworkβ Make satasii driver more robust

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Submitter Carl-Daniel Hailfinger
Date 2010-05-21 23:42:46
Message ID <4BF71A76.6030201@gmx.net>
Download mbox | patch
Permalink /patch/1370/
State Superseded
Headers show

Comments

Carl-Daniel Hailfinger - 2010-05-21 23:42:46
Make the satasii driver more robust.

Untested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Rudolf Marek - 2010-05-22 22:13:25
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Hi thanks for doing that.

Carl-Daniel Hailfinger wrote:
> Make the satasii driver more robust.
> 
> Untested.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
> 
> Index: flashrom-satasii_robust/satasii.c
> ===================================================================
> --- flashrom-satasii_robust/satasii.c	(Revision 1005)
> +++ flashrom-satasii_robust/satasii.c	(Arbeitskopie)
> @@ -44,6 +44,7 @@
>  {
>  	uint32_t addr;
>  	uint16_t reg_offset;
> +	uint32_t tmp;
>  
>  	get_io_perms();
>  
> @@ -59,12 +60,19 @@
>  		reg_offset = 0x50;
>  	}
>  
> -	sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
> +	sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset;
>  
>  	/* Check if ROM cycle are OK. */
>  	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
>  		msg_pinfo("Warning: Flash seems unconnected.\n");
>  
> +	msg_pdbg("Using BAR5 access method.\n");
> +	tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1);
> +	msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis");
> +	/* This bit has contradicting definitions in the 3512 datasheet. */

this looks strange you get dissnabled or ensabled ;)

> +	tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16);
> +	msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis");

This Reg is EN_66 in other controllers so I guess it just this and not the
BA5_EN. It looks like it is driven by strap resistor only anyway.

Interesting would be to test if BA5_EN is not enabled if you can access it
through indirect access through C0/C4 regs.

Thanks,
Rudolf


> +
>  	buses_supported = CHIP_BUSTYPE_PARALLEL;
>  
>  	return 0;
> @@ -81,6 +89,7 @@
>  void satasii_chip_writeb(uint8_t val, chipaddr addr)
>  {
>  	uint32_t ctrl_reg, data_reg;
> +	int i = 0;
>  
>  	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>  
> @@ -92,12 +101,19 @@
>  	mmio_writel(data_reg, (sii_bar + 4));
>  	mmio_writel(ctrl_reg, sii_bar);
>  
> -	while (mmio_readl(sii_bar) & (1 << 25)) ;
> +	while (mmio_readl(sii_bar) & (1 << 25)) {
> +		if (++i > 10000) {
> +			msg_perr("%s: control reg stuck at %08x, aborting\n",
> +				 __func__, mmio_readl(sii_bar));
> +			break;
> +		}
> +	}
>  }
>  
>  uint8_t satasii_chip_readb(const chipaddr addr)
>  {
>  	uint32_t ctrl_reg;
> +	int i = 0;
>  
>  	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>  
> @@ -107,7 +123,13 @@
>  
>  	mmio_writel(ctrl_reg, sii_bar);
>  
> -	while (mmio_readl(sii_bar) & (1 << 25)) ;
> +	while (mmio_readl(sii_bar) & (1 << 25)) {
> +		if (++i > 10000) {
> +			msg_perr("%s: control reg stuck at %08x, aborting\n",
> +				 __func__, mmio_readl(sii_bar));
> +			break;
> +		}
> +	}
>  
>  	return (mmio_readl(sii_bar + 4)) & 0xff;
>  }
> 
> 
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Patch

Index: flashrom-satasii_robust/satasii.c
===================================================================
--- flashrom-satasii_robust/satasii.c	(Revision 1005)
+++ flashrom-satasii_robust/satasii.c	(Arbeitskopie)
@@ -44,6 +44,7 @@ 
 {
 	uint32_t addr;
 	uint16_t reg_offset;
+	uint32_t tmp;
 
 	get_io_perms();
 
@@ -59,12 +60,19 @@ 
 		reg_offset = 0x50;
 	}
 
-	sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
+	sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset;
 
 	/* Check if ROM cycle are OK. */
 	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
 		msg_pinfo("Warning: Flash seems unconnected.\n");
 
+	msg_pdbg("Using BAR5 access method.\n");
+	tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1);
+	msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis");
+	/* This bit has contradicting definitions in the 3512 datasheet. */
+	tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16);
+	msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis");
+
 	buses_supported = CHIP_BUSTYPE_PARALLEL;
 
 	return 0;
@@ -81,6 +89,7 @@ 
 void satasii_chip_writeb(uint8_t val, chipaddr addr)
 {
 	uint32_t ctrl_reg, data_reg;
+	int i = 0;
 
 	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
 
@@ -92,12 +101,19 @@ 
 	mmio_writel(data_reg, (sii_bar + 4));
 	mmio_writel(ctrl_reg, sii_bar);
 
-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_readl(sii_bar) & (1 << 25)) {
+		if (++i > 10000) {
+			msg_perr("%s: control reg stuck at %08x, aborting\n",
+				 __func__, mmio_readl(sii_bar));
+			break;
+		}
+	}
 }
 
 uint8_t satasii_chip_readb(const chipaddr addr)
 {
 	uint32_t ctrl_reg;
+	int i = 0;
 
 	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
 
@@ -107,7 +123,13 @@ 
 
 	mmio_writel(ctrl_reg, sii_bar);
 
-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_readl(sii_bar) & (1 << 25)) {
+		if (++i > 10000) {
+			msg_perr("%s: control reg stuck at %08x, aborting\n",
+				 __func__, mmio_readl(sii_bar));
+			break;
+		}
+	}
 
 	return (mmio_readl(sii_bar + 4)) & 0xff;
 }