Index: flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c
===================================================================
--- flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c	(Revision 1035)
+++ flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c	(Arbeitskopie)
@@ -728,16 +728,12 @@
 
 /**
  * Geode systems write protect the BIOS via RCONFs (cache settings similar
- * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. 
- *
- * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
- * To enable write to NOR Boot flash for the benefit of systems that have such
- * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
+ * FIXME: Is this only for Geode LX or also for other Geode models?
  */
-static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+static int enable_flash_geode(void)
 {
 #define MSR_RCONF_DEFAULT	0x1808
-#define MSR_NORF_CTL		0x51400018
 
 	msr_t msr;
 
@@ -751,6 +747,30 @@
 		wrmsr(MSR_RCONF_DEFAULT, msr);
 	}
 
+	cleanup_cpu_msr();
+
+#undef MSR_RCONF_DEFAULT
+	return 0;
+}
+
+/**
+ * CS5536 systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
+ * To enable write to NOR Boot flash for the benefit of systems that have such
+ * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ */
+static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+{
+#define MSR_NORF_CTL		0x51400018
+
+	msr_t msr;
+
+	if (enable_flash_geode())
+		return -1;
+
+	/* Geode only has a single core */
+	if (setup_cpu_msr(0))
+		return -1;
+
 	msr = rdmsr(MSR_NORF_CTL);
 	/* Raise WE_CS3 bit. */
 	msr.lo |= 0x08;
@@ -758,7 +778,6 @@
 
 	cleanup_cpu_msr();
 
-#undef MSR_RCONF_DEFAULT
 #undef MSR_NORF_CTL
 	return 0;
 }