Patchworkβ Wyse S50 RAMBASE 0x100000 fix

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Submitter Nils
Date 2010-06-07 22:55:58
Message ID <201006080055.58504.njacobs8@hetnet.nl>
Download mbox | patch
Permalink /patch/1485/
State Superseded
Headers show

Comments

Nils - 2010-06-07 22:55:58
This patch fixes RAMBASE 0x100000 for Wyse S50.
I think that the problem was that extended memory was not setup early enough.
This patch is boot tested on r5621.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>

And now with patch attached,sorry.

Thanks,Nils.
Patrick Georgi - 2010-06-08 06:01:23
Am 08.06.2010 00:55, schrieb Nils:
> This patch fixes RAMBASE 0x100000 for Wyse S50.
> I think that the problem was that extended memory was not setup early enough.
Looks plausible.
Is there a reason why this function is mainboard specific? It seems to
me that this, including your change, should be part of the chipset code.

> This patch is boot tested on r5621.
> 
> Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Stefan Reinauer - 2010-06-08 08:54:00
On 6/8/10 12:55 AM, Nils wrote:
> +	__builtin_wrmsr(MSR_GLIU1_SYSMEM, 0x6bf00100, 0x2000001f); /*	0x100000-0x1F6BF000 */
>   
Why 1F6BF000 ?

Stefan

Patch

Index: src/mainboard/wyse/s50/Kconfig
===================================================================
--- src/mainboard/wyse/s50/Kconfig	(revision 5621)
+++ src/mainboard/wyse/s50/Kconfig	(working copy)
@@ -48,8 +48,3 @@ 
 	int
 	default 3
 	depends on BOARD_WYSE_S50
-
-config RAMBASE
-	hex
-	default 0x4000
-	depends on BOARD_WYSE_S50
Index: src/mainboard/wyse/s50/romstage.c
===================================================================
--- src/mainboard/wyse/s50/romstage.c	(revision 5621)
+++ src/mainboard/wyse/s50/romstage.c	(working copy)
@@ -1,3 +1,4 @@ 
+
 /*
  * This file is part of the coreboot project.
  *
@@ -136,13 +137,15 @@ 
 	__builtin_wrmsr(CPU_RCONF_C0_DF,  0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */
 	__builtin_wrmsr(CPU_RCONF_E0_FF,  0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */
 	
-	/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
+	/* Setup access to memory. Note: VGA hole at 0xA0000-0xBFFFF */
 	__builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /*	0x00000-0x7FFFF */
 	__builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /*	0x80000-0x9FFFF */
 	__builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /*	0xC0000-0xFFFFF */
+	__builtin_wrmsr(MSR_GLIU0_SYSMEM, 0x6bf00100, 0x2000001f); /*	0x100000-0x1F6BF000 */
 	__builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /*	0x00000-0x7FFFF */
 	__builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /*	0x80000-0x9FFFF */
 	__builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /*	0xC0000-0xFFFFF */
+	__builtin_wrmsr(MSR_GLIU1_SYSMEM, 0x6bf00100, 0x2000001f); /*	0x100000-0x1F6BF000 */
 
 	/* put code in northbridge[init].c here */
 }