Patchwork ICH6-ICH10 flash decode debug

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Submitter Carl-Daniel Hailfinger
Date 2009-08-10 11:06:26
Message ID <4A7FFF32.4070808@gmx.net>
Download mbox | patch
Permalink /patch/101/
State Accepted
Commit r675
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Comments

Carl-Daniel Hailfinger - 2009-08-10 11:06:26
Chris, can you please test this one? It doesn't contain the fix, but it
has all the debug output. Basically, this is the mergeable part, and
once this is committed, it's a lot easier for me to work on the real
fix. Plus, the hack to get it going is a mere one-liner after this. What
I'd need to get this committed are the output lines mentioning FWH
IDSEL/decode. Thanks!

Regards,
Carl-Daniel


Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode
settings to the debug output. This can help debug cases where the BIOS
does not set up a correct flash decode for the given flash size.
The Intel docs state that the decode applies to FWH and SPI flash.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Chris Kinney - 2009-08-10 23:28:31
Acked-by: Chris Kinney <cmkinne@sandia.gov>

Carl-Daniel Hailfinger wrote:
> Chris, can you please test this one? It doesn't contain the fix, but it
> has all the debug output. Basically, this is the mergeable part, and
> once this is committed, it's a lot easier for me to work on the real
> fix. Plus, the hack to get it going is a mere one-liner after this. What
> I'd need to get this committed are the output lines mentioning FWH
> IDSEL/decode. Thanks!
>
> Regards,
> Carl-Daniel
>
>
> Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode
> settings to the debug output. This can help debug cases where the BIOS
> does not set up a correct flash decode for the given flash size.
> The Intel docs state that the decode applies to FWH and SPI flash.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
>
> Index: flashrom-ich6_fwh_idsel_debug/chipset_enable.c
> ===================================================================
> --- flashrom-ich6_fwh_idsel_debug/chipset_enable.c	(Revision 674)
> +++ flashrom-ich6_fwh_idsel_debug/chipset_enable.c	(Arbeitskopie)
> @@ -191,11 +191,47 @@
>  
>  static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
>  {
> +	/*
> +	 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
> +	 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
> +	 * FB_DEC_EN2.
> +	 */
>  	return enable_flash_ich(dev, name, 0x4e);
>  }
>  
>  static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
>  {
> +	uint32_t fwh_conf;
> +	int i;
> +
> +	/* Ignore all legacy ranges below 1 MB. */
> +	/* FWH_SEL1 */
> +	fwh_conf = pci_read_long(dev, 0xd0);
> +	for (i = 7; i >= 0; i--)
> +		printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
> +			     (0x1ff8 + i) * 0x80000,
> +			     (0x1ff0 + i) * 0x80000,
> +			     (fwh_conf >> (i * 4)) & 0xf);
> +	/* FWH_SEL2 */
> +	fwh_conf = pci_read_word(dev, 0xd4);
> +	for (i = 3; i >= 0; i--)
> +		printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
> +			     (0xff4 + i) * 0x100000,
> +			     (0xff0 + i) * 0x100000,
> +			     (fwh_conf >> (i * 4)) & 0xf);
> +	/* FWH_DEC_EN1 */
> +	fwh_conf = pci_read_word(dev, 0xd8);
> +	for (i = 7; i >= 0; i--)
> +		printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
> +			     (0x1ff8 + i) * 0x80000,
> +			     (0x1ff0 + i) * 0x80000,
> +			     (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
> +	for (i = 3; i >= 0; i--)
> +		printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
> +			     (0xff4 + i) * 0x100000,
> +			     (0xff0 + i) * 0x100000,
> +			     (fwh_conf >> i) & 0x1 ? "en" : "dis");
> +
>  	return enable_flash_ich(dev, name, 0xdc);
>  }
>  
>
>
>
Carl-Daniel Hailfinger - 2009-08-10 23:31:47
On 11.08.2009 01:28, Chris Kinney wrote:
> Acked-by: Chris Kinney <cmkinne@sandia.gov>
>
> Carl-Daniel Hailfinger wrote:
>> Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode
>> settings to the debug output. This can help debug cases where the BIOS
>> does not set up a correct flash decode for the given flash size.
>> The Intel docs state that the decode applies to FWH and SPI flash.
>>
>> Signed-off-by: Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006@gmx.net>

Thanks, committed in r675.

Regards,
Carl-Daniel

Patch

Index: flashrom-ich6_fwh_idsel_debug/chipset_enable.c
===================================================================
--- flashrom-ich6_fwh_idsel_debug/chipset_enable.c	(Revision 674)
+++ flashrom-ich6_fwh_idsel_debug/chipset_enable.c	(Arbeitskopie)
@@ -191,11 +191,47 @@ 
 
 static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
 {
+	/*
+	 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
+	 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
+	 * FB_DEC_EN2.
+	 */
 	return enable_flash_ich(dev, name, 0x4e);
 }
 
 static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
 {
+	uint32_t fwh_conf;
+	int i;
+
+	/* Ignore all legacy ranges below 1 MB. */
+	/* FWH_SEL1 */
+	fwh_conf = pci_read_long(dev, 0xd0);
+	for (i = 7; i >= 0; i--)
+		printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
+			     (0x1ff8 + i) * 0x80000,
+			     (0x1ff0 + i) * 0x80000,
+			     (fwh_conf >> (i * 4)) & 0xf);
+	/* FWH_SEL2 */
+	fwh_conf = pci_read_word(dev, 0xd4);
+	for (i = 3; i >= 0; i--)
+		printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
+			     (0xff4 + i) * 0x100000,
+			     (0xff0 + i) * 0x100000,
+			     (fwh_conf >> (i * 4)) & 0xf);
+	/* FWH_DEC_EN1 */
+	fwh_conf = pci_read_word(dev, 0xd8);
+	for (i = 7; i >= 0; i--)
+		printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
+			     (0x1ff8 + i) * 0x80000,
+			     (0x1ff0 + i) * 0x80000,
+			     (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
+	for (i = 3; i >= 0; i--)
+		printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
+			     (0xff4 + i) * 0x100000,
+			     (0xff0 + i) * 0x100000,
+			     (fwh_conf >> i) & 0x1 ? "en" : "dis");
+
 	return enable_flash_ich(dev, name, 0xdc);
 }