From patchwork Fri Mar 5 16:53:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Tyan S2912 Fam10 Date: Fri, 05 Mar 2010 16:53:07 -0000 From: Arne Georg Gleditsch X-Patchwork-Id: 1014 Message-Id: <4B9136F3.6090003@numascale.com> To: coreboot@coreboot.org (Hm, this message seems to not have made it through. Resending...) Hi all, I've just recently brought my development environment up to speed with the latest coreboot version -- which is very nice! -- and caught a couple of minor issues. I'm not sure I fully understand the underlying logic behind the different CAR setup routines in src/cpu/amd/car/cache_as_ram.inc, but the attached patch is required to make the S2912 board choose the correct code path. I've also upped the MAX_CPUS setting to 12 to accommodate 6-core Istanbul CPUs. This might make sense for other fam10 boards as well. Signed-off-by: Arne Georg Gleditsch Acked-by: Patrick Georgi diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 91f8f45..b3c4c4f 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -38,6 +38,26 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE default 0x04000 depends on BOARD_TYAN_S2912_FAM10 +config USE_FALLBACK_IMAGE + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + +config HAVE_FALLBACK_BOOT + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + +config CONFIG_USE_FAILOVER_IMAGE + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + +config CONFIG_HAVE_FAILOVER_BOOT + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + config APIC_ID_OFFSET hex default 0 @@ -95,7 +115,7 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 8 + default 12 depends on BOARD_TYAN_S2912_FAM10 config MAX_PHYSICAL_CPUS