| Submitter | Stefan Reinauer |
|---|---|
| Date | 2010-03-08 18:38:51 |
| Message ID | <4B95443B.3050501@coresystems.de> |
| Download | mbox | patch |
| Permalink | /patch/1025/ |
| State | Not Applicable, archived |
| Headers | show |
Comments
argl, forward this to coreboot list too. ---------- Forwarded message ---------- From: Karl-Heinz Nirschl <kh.nirschl@googlemail.com> Date: 2010/3/8 Subject: Re: [coreboot] Getting started with Coreboot on Intel Core To: Stefan Reinauer <stepan@coresystems.de> Hi, thanks for your reply. i thought src/northbridge/intel/i945/early_init.c is executed after stage1_main somewhere in real main. i've put a lot of postcodes bevor that - one in front of stage1_main and and one in real_main. shouldn't i see these? in my understanding execution takes the following way: 1 some generic x86 startup assembler 2 cache_as_ram.inc 3 cache_as_ram_disable.inc (stage1_main) 4 romstage.c (real_main) in mainboard dir 5 cpu_init 6 nb_init -... isn't that right? it looks like i hang between 2 und 3. i'll go and check the toolschain in utils. best regards, khn 2010/3/8 Stefan Reinauer <stepan@coresystems.de>: > On 3/8/10 6:36 PM, Karl-Heinz Nirschl wrote: >> Hi, >> >> i should append: >> >> this is using a spi flash with 2 Megs and todays svn version. >> i also tried with a 1 meg fhw with a somewhat earlier version of >> coreboot. same problem. >> >> >> regards, >> >> karl >> >> >> >> 2010/3/8 Karl-Heinz Nirschl <kh.nirschl@googlemail.com>: >> >>> Hi there, >>> >>> i'm new to coreboot and trying to port coreboot to a intel core based >>> board. it's a u2500 with a ich7m and 945gm. >>> i started with kontron 986lcd-m which should be quite similar but >>> didn't have much success so far. >>> > Did you adapt the code for your SuperIO chip? Do you get any messages on > the serial port? > >>> the board hangs with post code 0x23 (pci post card) which is bevor >>> "call stage1_main" in model_6ex/cache_as_ram.inc. >>> >>> as this is very early and the cpu never seem to come to stage1_main >>> (in cache_as_ram_disable.c) i assume i have a problem with my >>> toolchain. >>> > > Try this one: > > Index: src/northbridge/intel/i945/early_init.c > =================================================================== > --- src/northbridge/intel/i945/early_init.c (revision 5196) > +++ src/northbridge/intel/i945/early_init.c (working copy) > @@ -867,7 +867,7 @@ > i945_setup_bars(); > > /* Change port80 to LPC */ > - RCBA32(GCS) &= (~0x04); > + //RCBA32(GCS) &= (~0x04); > > /* Just do it that way */ > RCBA32(0x2010) |= (1 << 10); > > Then post codes keep going to PCI instead of LPC and you should see > where it's going. > > > > > >>> I build on ubuntu 8.04 (Hardy Heron) with nothing special. >>> >>> Any hints for a coreboot newbie? Which additional information could i >>> provide to find the problem? >>> > > You should use the reference toolchain in util/crossgcc > > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info@coresystems.de • http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg • HRB 7656 > Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >
On 3/8/10 9:45 PM, Karl-Heinz Nirschl wrote: > Hi, > > thanks for your reply. i thought > src/northbridge/intel/i945/early_init.c is executed after stage1_main > somewhere in real main. i've put a lot of postcodes bevor that > - one in front of stage1_main and and one in real_main. shouldn't i see these? > From your description I can't tell. But 0x23 is the last post code before the call into stage1_main(). stage1_main() calls real_main() which calls into early_init.c., Stefan
On 3/8/10 10:48 PM, Karl-Heinz Nirschl wrote: > Hi, > > i've just compiled the crossgcc. but how do i make the build system > use it. is there a coreboot way of doing it? > > coreboot should just pick it up... the script util/xcompile/xcompile should create an according .xcompile file in the coreboot root directory Stefan
On Mon, 08 Mar 2010 23:04:11 +0100, Stefan Reinauer <stepan@coresystems.de> wrote: > On 3/8/10 10:48 PM, Karl-Heinz Nirschl wrote: >> Hi, >> >> i've just compiled the crossgcc. but how do i make the build system >> use it. is there a coreboot way of doing it? >> >> > coreboot should just pick it up... the script util/xcompile/xcompile > should create an according .xcompile file in the coreboot root directory > huh? So it just dosen't look for it in your $PATH???
On 3/9/10 1:02 AM, Joseph Smith wrote: > > > On Mon, 08 Mar 2010 23:04:11 +0100, Stefan Reinauer <stepan@coresystems.de> > wrote: > >> On 3/8/10 10:48 PM, Karl-Heinz Nirschl wrote: >> >>> Hi, >>> >>> i've just compiled the crossgcc. but how do i make the build system >>> use it. is there a coreboot way of doing it? >>> >>> >>> >> coreboot should just pick it up... the script util/xcompile/xcompile >> should create an according .xcompile file in the coreboot root directory >> >> > huh? > So it just dosen't look for it in your $PATH??? > > It does, right after it checked util/crossgcc/xgcc/bin
On Tue, 09 Mar 2010 01:23:34 +0100, Stefan Reinauer <stepan@coresystems.de> wrote: > On 3/9/10 1:02 AM, Joseph Smith wrote: >> >> >> On Mon, 08 Mar 2010 23:04:11 +0100, Stefan Reinauer > <stepan@coresystems.de> >> wrote: >> >>> On 3/8/10 10:48 PM, Karl-Heinz Nirschl wrote: >>> >>>> Hi, >>>> >>>> i've just compiled the crossgcc. but how do i make the build system >>>> use it. is there a coreboot way of doing it? >>>> >>>> >>>> >>> coreboot should just pick it up... the script util/xcompile/xcompile >>> should create an according .xcompile file in the coreboot root directory >>> >>> >> huh? >> So it just dosen't look for it in your $PATH??? >> >> > It does, right after it checked util/crossgcc/xgcc/bin > oh ok.
Hi, no i use crossgcc which looks fine, but still can't hang with postcode 0x23. if have the following in crt0.disasm: 153 0148 B023E680 post_code(0x23) 154 155 014c E8FCFFFF call stage1_main 155 FF and the following in romstage.inc (both from build dir): stage1_main: subl $24, %esp /APP / 29 "/home/xxx/coreboot/src/cpu/intel/model_6ex/cache_as_ram_disable.c" 1 movb 0xa4, %al outb %al, $0x80 so i suppose i should at least see postcode 0xa4 if the call instruction succeeds. any further hints what i could have done wrong? regards, khn
Hi, i still haven't found whats wrong. toolchain seems to be ok, as everything works fine with qemu. could someone confirm that kontron 986lcd-m is working in the current svn version? regards, karl 2010/3/9 Karl-Heinz Nirschl <kh.nirschl@googlemail.com>: > Hi, > > no i use crossgcc which looks fine, but still can't hang with postcode 0x23. > > if have the following in crt0.disasm: > 153 0148 B023E680 post_code(0x23) > 154 > 155 014c E8FCFFFF call stage1_main > 155 FF > > and the following in romstage.inc (both from build dir): > > stage1_main: > subl $24, %esp > /APP > / 29 "/home/xxx/coreboot/src/cpu/intel/model_6ex/cache_as_ram_disable.c" 1 > movb 0xa4, %al > outb %al, $0x80 > > so i suppose i should at least see postcode 0xa4 if the call > instruction succeeds. > > any further hints what i could have done wrong? > > > regards, > > khn >
Patch
Index: src/northbridge/intel/i945/early_init.c =================================================================== --- src/northbridge/intel/i945/early_init.c (revision 5196) +++ src/northbridge/intel/i945/early_init.c (working copy) @@ -867,7 +867,7 @@ i945_setup_bars(); /* Change port80 to LPC */ - RCBA32(GCS) &= (~0x04); + //RCBA32(GCS) &= (~0x04); /* Just do it that way */ RCBA32(0x2010) |= (1 << 10);