Polish the flashrom code comments and outputs a bit.
- Fix a number of typos (found via ispell).
- Use correct vendor names (as per their websites) consistently.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
===================================================================
@@ -174,7 +174,7 @@
Show version information and exit.
.SH PROGRAMMER SPECIFIC INFO
Some programmer drivers accept further parameters to set programmer-specific
-parameters. These parameters are seperated from the programmer name by a
+parameters. These parameters are separated from the programmer name by a
colon. While some programmers take arguments at fixed positions, other
programmers use a key/value interface in which the key and value is separated
by an equal sign and different pairs are separated by a comma or a colon.
@@ -289,8 +289,8 @@
the source distribution.
.TP
.BR "buspiratespi " programmer
-A required dev parameter specifyies the Bus Pirate device node and an optional
-spispeed parameter specifyies the frequency of the SPI bus. The parameter
+A required dev parameter specifies the Bus Pirate device node and an optional
+spispeed parameter specifies the frequency of the SPI bus. The parameter
delimiter is a comma. Syntax is
.sp
.B "flashrom -p buspiratespi:dev=/dev/device,spispeed=frequency"
===================================================================
@@ -345,7 +345,7 @@
chipaddr d = dst;
retry:
- /* Issue JEDEC Start Program comand */
+ /* Issue JEDEC Start Program command */
start_program_jedec_common(flash, mask);
/* transfer data from source to destination */
===================================================================
@@ -27,11 +27,11 @@
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
- * other means, such as quering the hardware directly.
+ * other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
- * without it's meaning/correctnes changing. For table that
+ * without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
@@ -48,7 +48,7 @@
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
- * dropped. Of course it is polite and expidite to include extra
+ * dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
@@ -78,10 +78,10 @@
uint32_t table_entries;
};
-/* Every entry in the boot enviroment list will correspond to a boot
+/* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that
- * boot enviroment record if you don't know what it easy. This allows
+ * boot environment record if you don't know what it easy. This allows
* forward compatibility with records not yet defined.
*/
struct lb_record {
===================================================================
@@ -46,14 +46,14 @@
cmd 7 support: byte 0 bit 7
cmd 8 support: byte 1 bit 0, and so on.
0x04 (Q_SERBUF):
- If the programmer has guaranteedly working flow control,
+ If the programmer has a guaranteed working flow control,
it should return a big bogus value - eg 0xFFFF.
0x05 (Q_BUSTYPE):
The bit's are defined as follows:
bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported).
0x06 (Q_CHIPSIZE):
Only applicable to parallel programmers.
- An LPC/FHW/SPI-programmer can report this as not supported in the command bitmap.
+ An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap.
0x08 (Q_WRNMAXLEN):
If a programmer reports a bigger maximum write-n length than the serial buffer size,
it is assumed that the programmer can process the data fast enough to take in the
===================================================================
@@ -66,7 +66,7 @@
/* Bitmap of supported commands */
static uint8_t sp_cmdmap[32];
-/* sp_prev_was_write used to detect writes with continouous addresses
+/* sp_prev_was_write used to detect writes with continuous addresses
and combine them to write-n's */
static int sp_prev_was_write = 0;
/* sp_write_n_addr used as the starting addr of the currently
@@ -138,7 +138,7 @@
return -1;
}
-/* Synchronize: a bit tricky algorhytm that tries to (and in my tests has *
+/* Synchronize: a bit tricky algorithm that tries to (and in my tests has *
* always succeeded in) bring the serial protocol to known waiting-for- *
* command state - uses nonblocking read - rest of the driver uses *
* blocking read - TODO: add an alarm() timer for the rest of the app on *
@@ -534,7 +534,7 @@
if (sp_device_opbuf_size <= (sp_opbuf_usage + bytes_to_be_added)) {
sp_execute_opbuf();
/* If this happens in the mid of an page load the page load *
- * will propably fail. */
+ * will probably fail. */
msg_pdbg(MSGHEADER "Warning: executed operation buffer due to size reasons\n");
}
}
@@ -589,7 +589,7 @@
return c;
}
-/* Local version that really does the job, doesnt care of max_read_n. */
+/* Local version that really does the job, doesn't care of max_read_n. */
static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len)
{
int rd_bytes = 0;
===================================================================
@@ -1133,7 +1133,7 @@
},
/* The next two chip definitions have top/bottom boot blocks, but has no
- device differenciation between the two */
+ device differentiation between the two */
{
.vendor = "AMIC",
.name = "A25L40PT",
===================================================================
@@ -69,7 +69,7 @@
* to them. The size of the locking sectors depends on the type
* of chip.
*
- * Sometimes, the BIOS does this for you; so you propably
+ * Sometimes, the BIOS does this for you; so you probably
* don't need to worry about that.
*/
===================================================================
@@ -102,6 +102,6 @@
#flashrom at irc.freenode.net
-The Mailing list addess is
+The Mailing list address is
flashrom@flashrom.org
===================================================================
@@ -536,7 +536,7 @@
/* clear error status registers */
temp32 |= (SSFS_CDS + SSFS_FCERR);
- /* USE 20 MhZ */
+ /* Use 20 MHz */
temp32 |= SSFC_SCF_20MHZ;
if (datalength != 0) {
===================================================================
@@ -330,7 +330,7 @@
}
/**
- * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
+ * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
*/
static int via_vt823x_gpio5_raise(const char *name)
{
@@ -339,7 +339,7 @@
}
/**
- * Suited for VIAs EPIA N & NL.
+ * Suited for VIA EPIA N & NL.
*/
static int via_vt823x_gpio9_raise(const char *name)
{
@@ -347,7 +347,7 @@
}
/**
- * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
+ * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs.
*
* We don't need to do this for EPIA M when using coreboot, GPIO15 is never
* lowered there.
@@ -473,7 +473,7 @@
}
/**
- * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4).
+ * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4).
*/
static int board_shuttle_fn25(const char *name)
{
@@ -521,7 +521,7 @@
break;
default:
fprintf(stderr,
- "\nERROR: no nVidia LPC/SMBus controller found.\n");
+ "\nERROR: no NVIDIA LPC/SMBus controller found.\n");
return -1;
}
break;
@@ -541,7 +541,7 @@
}
/**
- * Suited for ASUS M2NBP-VM CSM: nVidia MCP51.
+ * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51.
*/
static int nvidia_mcp_gpio0_raise(const char *name)
{
@@ -549,8 +549,8 @@
}
/**
- * Suited for MSI K8N Neo4: nVidia CK804.
- * Suited for MSI K8N GM2-L: nVidia MCP51.
+ * Suited for MSI K8N Neo4: NVIDIA CK804.
+ * Suited for MSI K8N GM2-L: NVIDIA MCP51.
*/
static int nvidia_mcp_gpio2_raise(const char *name)
{
@@ -623,7 +623,7 @@
}
/**
- * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M}
+ * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
*/
static int intel_piix4_gpo_set(unsigned int gpo, int raise)
{
@@ -703,11 +703,11 @@
}
/**
- * Set a GPIO line on a given intel ICH LPC controller.
+ * Set a GPIO line on a given Intel ICH LPC controller.
*/
static int intel_ich_gpio_set(int gpio, int raise)
{
- /* table mapping the different intel ICH LPC chipsets. */
+ /* Table mapping the different Intel ICH LPC chipsets. */
static struct {
uint16_t id;
uint8_t base_reg;
@@ -773,8 +773,8 @@
return -1;
}
- /* According to the datasheets, all intel ICHs have the gpio bar 5:1
- strapped to zero. From some mobile ich9 version on, this becomes
+ /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
+ strapped to zero. From some mobile ICH9 version on, this becomes
6:1. The mask below catches all. */
base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
@@ -913,9 +913,9 @@
/**
* Suited for:
- * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
- * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5.
- * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
+ * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
+ * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5.
+ * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
*/
static int intel_ich_gpio21_raise(const char *name)
{
@@ -924,8 +924,8 @@
/**
* Suited for:
- * - Asus P4B266: socket478 + intel 845D + ICH2.
- * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
+ * - ASUS P4B266: socket478 + intel 845D + ICH2.
+ * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
*/
static int intel_ich_gpio22_raise(const char *name)
{
@@ -949,7 +949,7 @@
/**
* Suited for:
- * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R.
+ * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R.
* - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
*/
static int intel_ich_gpio23_raise(const char *name)
@@ -1116,7 +1116,7 @@
}
/**
- * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
+ * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A
*/
static int board_asus_a7v8x(const char *name)
{
@@ -1210,8 +1210,8 @@
/**
* Suited for:
- * - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
- * - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F
+ * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
+ * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
*/
static int it8712f_gpio3_1_raise(const char *name)
{
@@ -1238,7 +1238,7 @@
*
* If PCI IDs are not sufficient for board matching, the match can be further
* constrained by a string that has to be present in the DMI database for
- * the baseboard or the system entry. The pattern is matched by case sensitve
+ * the baseboard or the system entry. The pattern is matched by case sensitive
* substring match, unless it is anchored to the beginning (with a ^ in front)
* or the end (with a $ at the end). Both anchors may be specified at the
* same time to match the full field.