Patchwork Remove failover/fallback/normal decision from mainboards' romstage.c

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Submitter Patrick Georgi
Date 2010-03-17 21:42:02
Message ID <4BA14CAA.8040807@georgi-clan.de>
Download mbox | patch
Permalink /patch/1081/
State Accepted
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Comments

Patrick Georgi - 2010-03-17 21:42:02
Hi,

attached patch removes the failover/fallback/normal decision from
romstage.c files of mainboards that did failover. It is the first part
of a larger effort.

This mechanism was used by newconfig style builds and is not useful
anymore since we dropped newconfig. In fact, in rare circumstances it
might lead to coreboot hanging early on boot (when normal is selected -
this should fix itself by three reboots, as coreboot reverts to fallback
then)

The code assumes that various places are visited twice on boot. That's
not true anymore for Kconfig builds, no matter if the boards is using
romstage as bootblock, or the tiny bootblock.
Removing these assumptions simplifies the code and should help the user
when trying to track the code flow.


The change looks big, but it's really a couple of simple and relatively
mechanical steps repeated for lots of boards:

1. In failover_process(), I removed the fallback/normal selection logic
and kept the remaining hardware init in. The if-clauses' conditions are
reverted to match.
Remove #if failover||fallback guard.

2. Change cache_as_ram_main() to first call failover_process, then
real_main unconditionally.

3. Move failover_process's code to the beginning of real_main, remove
failover_process and its call in cache_as_ram_main.

4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
arguments, so no problem with that)

As those changes are quite mechanical, but not easily automated, I'd
prefer some additional eyeballs that look if the end result of the
boards looks alike (they should be more similar to each other than before).

The patch is build tested and boot tested on amd/serengeti_cheetah in
SimNow.


After the changes, the entire hardware init is ran on cold boot, on warm
reset the hardware init that used to be in failover_process is skipped.

The affected boards do not use __fallback_image or __normal_image anymore.


The next step will a comparable change to the remaining boards.

After that, I'll aim for the removal of the remaining uses of
HAVE_FALLBACK_BOOT, USE_FALLBACK_IMAGE,
HAVE_FAILOVER_BOOT, USE_FAILOVER_IMAGE and their definition in Kconfig.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Index: src/arch/i386/lib/failover_failover.lds (deleted)
===================================================================
Stefan Reinauer - 2010-03-17 22:19:31
On 3/17/10 10:42 PM, Patrick Georgi wrote:
> Hi,
>
> attached patch removes the failover/fallback/normal decision from
> romstage.c files of mainboards that did failover. It is the first part
> of a larger effort.
>
> This mechanism was used by newconfig style builds and is not useful
> anymore since we dropped newconfig. In fact, in rare circumstances it
> might lead to coreboot hanging early on boot (when normal is selected -
> this should fix itself by three reboots, as coreboot reverts to fallback
> then)
>
> The code assumes that various places are visited twice on boot. That's
> not true anymore for Kconfig builds, no matter if the boards is using
> romstage as bootblock, or the tiny bootblock.
> Removing these assumptions simplifies the code and should help the user
> when trying to track the code flow.
>
>
> The change looks big, but it's really a couple of simple and relatively
> mechanical steps repeated for lots of boards:
>
> 1. In failover_process(), I removed the fallback/normal selection logic
> and kept the remaining hardware init in. The if-clauses' conditions are
> reverted to match.
> Remove #if failover||fallback guard.
>
> 2. Change cache_as_ram_main() to first call failover_process, then
> real_main unconditionally.
>
> 3. Move failover_process's code to the beginning of real_main, remove
> failover_process and its call in cache_as_ram_main.
>
> 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
> arguments, so no problem with that)
>
> As those changes are quite mechanical, but not easily automated, I'd
> prefer some additional eyeballs that look if the end result of the
> boards looks alike (they should be more similar to each other than before).
>
> The patch is build tested and boot tested on amd/serengeti_cheetah in
> SimNow.
>
>
> After the changes, the entire hardware init is ran on cold boot, on warm
> reset the hardware init that used to be in failover_process is skipped.
>
> The affected boards do not use __fallback_image or __normal_image anymore.
>
>
> The next step will a comparable change to the remaining boards.
>
> After that, I'll aim for the removal of the remaining uses of
> HAVE_FALLBACK_BOOT, USE_FALLBACK_IMAGE,
> HAVE_FAILOVER_BOOT, USE_FAILOVER_IMAGE and their definition in Kconfig.
>
>
> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
>   
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Patch

Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c	(revision 5251)
+++ src/mainboard/iwill/dk8_htx/romstage.c	(working copy)
@@ -130,83 +130,13 @@ 
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        /* Setup the rom access for 4M */
-        amd8111_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 			//first node
                         DIMM0, DIMM2, 0, 0,
@@ -224,6 +154,16 @@ 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		/* Setup the rom access for 4M */
+		amd8111_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c	(revision 5251)
+++ src/mainboard/iwill/dk8s2/romstage.c	(working copy)
@@ -130,83 +130,13 @@ 
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        /* Setup the rom access for 4M */
-        amd8111_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 			//first node
                         DIMM0, DIMM2, 0, 0,
@@ -224,6 +154,16 @@ 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		/* Setup the rom access for 4M */
+		amd8111_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c	(revision 5251)
+++ src/mainboard/iwill/dk8x/romstage.c	(working copy)
@@ -130,83 +130,13 @@ 
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        /* Setup the rom access for 4M */
-        amd8111_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 			//first node
                         DIMM0, DIMM2, 0, 0,
@@ -224,6 +154,16 @@ 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		/* Setup the rom access for 4M */
+		amd8111_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/romstage.c	(revision 5251)
+++ src/mainboard/supermicro/h8dmr/romstage.c	(working copy)
@@ -139,8 +139,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -169,78 +167,10 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the mcp55 */
-        mcp55_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -255,6 +185,18 @@ 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c	(revision 5251)
+++ src/mainboard/supermicro/h8dme/romstage.c	(working copy)
@@ -193,8 +193,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -223,78 +221,13 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 last_boot_normal_x = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the mcp55 */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	} else {
-		goto fallback_image;
-	}
-normal_image:
-	__asm__ volatile ("jmp __normal_image":	/* outputs */
-			  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-	    );
-
-      fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image":	/* outputs */
-			  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-	    )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-#if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-#else
-	real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
 #define RC0 (2<<8)
 #define RC1 (1<<8)
 
 #if CONFIG_USE_FAILOVER_IMAGE==0
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
    don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
@@ -319,6 +252,18 @@ 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+	}
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	}
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	(revision 5251)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c	(working copy)
@@ -135,8 +135,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -165,81 +163,12 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        set_bsp_node_CHtExtNodeCfgEn();
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the mcp55 */
-        mcp55_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
@@ -248,6 +177,19 @@ 
 	u32 wants_reset;
 	msr_t msr;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+        }
+
   post_code(0x30);
  
         if (bist == 0) {
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	(revision 5251)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c	(working copy)
@@ -138,8 +138,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -168,75 +166,6 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        set_bsp_node_CHtExtNodeCfgEn();
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the mcp55 */
-        mcp55_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
@@ -282,7 +211,7 @@ 
 	pnp_exit_ext_func_mode(GPIO3_DEV);
 }
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
@@ -291,6 +220,19 @@ 
 	u32 wants_reset;
 	msr_t msr;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+        }
+
   post_code(0x30);
  
         if (bist == 0) {
Index: src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/romstage.c	(revision 5251)
+++ src/mainboard/gigabyte/m57sli/romstage.c	(working copy)
@@ -150,8 +150,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -176,78 +174,11 @@ 
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
 
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the mcp55 */
-        mcp55_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -263,6 +194,18 @@ 
         unsigned bsp_apicid = 0;
 	uint8_t tmp = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(revision 5251)
+++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(working copy)
@@ -152,9 +152,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
-#include "southbridge/sis/sis966/sis966_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 
@@ -178,78 +175,10 @@ 
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the sis966 */
-        sis966_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -264,6 +193,18 @@ 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the sis966 */
+		sis966_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c	(revision 5251)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c	(working copy)
@@ -154,83 +154,13 @@ 
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        enumerate_ht_chain();
-
-        /* Setup the rom access for 4M */
-        amd8111_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 			//first node
                         RC0|DIMM0, RC0|DIMM2, 0, 0,
@@ -259,6 +189,16 @@ 
 	struct cpuid_result cpuid1;
 #endif
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		/* Setup the rom access for 4M */
+		amd8111_enable_rom();
+        }
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c	(revision 5251)
+++ src/mainboard/amd/mahogany_fam10/romstage.c	(working copy)
@@ -131,80 +131,9 @@ 
 #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
 
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	int last_boot_normal_flag = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_flag) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	/* mov bsp to bus 0xff when > 8 nodes */
-	set_bsp_node_CHtExtNodeCfgEn();
-	enumerate_ht_chain();
-
-	sb700_pci_port80();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_flag) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
-
-normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		 : /* outputs */
-		 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
-fallback_image:
- #if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		 : /* outputs */
-		 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
- #endif
-	;
-}
-#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
-
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
- #else
-	real_main(bist, cpu_init_detectedx);
- #endif
-#else
- #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
- #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if (CONFIG_USE_FAILOVER_IMAGE==0)
 //#include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
@@ -218,7 +147,7 @@ 
 #define DIMM2 0x52
 #define DIMM3 0x53
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -227,6 +156,16 @@ 
 	u32 val;
 	msr_t msr;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sb700_pci_port80();
+	}
+
 	post_code(0x30);
 
 	if (bist == 0) {
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(revision 5251)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(working copy)
@@ -144,88 +144,15 @@ 
 #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
 
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	int last_boot_normal_flag = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_flag) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	/* mov bsp to bus 0xff when > 8 nodes */
-	set_bsp_node_CHtExtNodeCfgEn();
-	enumerate_ht_chain();
-
-	/* Setup the rom access for 4M */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_flag) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
-
-normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		 : /* outputs */
-		 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
-fallback_image:
- #if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		 : /* outputs */
-		 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
- #endif
-	;
-}
-#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
-
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
- #else
-	real_main(bist, cpu_init_detectedx);
- #endif
-#else
- #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
- #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-
 #if (CONFIG_USE_FAILOVER_IMAGE==0)
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -233,6 +160,17 @@ 
 	u32 val;
 	msr_t msr;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		/* Setup the rom access for 4M */
+		amd8111_enable_rom();
+	}
+
 	post_code(0x30);
 
 	if (bist == 0) {
Index: src/mainboard/hp/dl145_g3/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g3/romstage.c	(revision 5251)
+++ src/mainboard/hp/dl145_g3/romstage.c	(working copy)
@@ -155,8 +155,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -197,79 +195,10 @@ 
 }
 #endif
 
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	 /* Is this a cpu only reset? Is this a secondary cpu? */
-	 if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal()) { // RTC already inited
-			goto normal_image; //normal_image;
-		} else {
-			goto fallback_image;
-		}
-	 }
-
-	 /* Nothing special needs to be done to find bus 0 */
-	 /* Allow the HT devices to be found */
-
-	 enumerate_ht_chain();
-	 bcm5785_enable_rom();
-	 bcm5785_enable_lpc();
-	 //enable RTC
-	pc87417_enable_dev(RTC_DEV);
-
-	 /* Is this a deliberate reset by the bios */
-
-	 if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	 }
-	 /* This is the primary cpu how should I boot? */
-	 else if (do_normal_boot()) {
-		goto normal_image;
-	 }
-	 else {
-		goto fallback_image;
-	 }
- normal_image:
-	 __asm__ volatile ("jmp __normal_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
-#endif
-	 ;
-
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 		//first node
 		 DIMM0, DIMM2, 0, 0,
@@ -287,7 +216,18 @@ 
 	 int needs_reset;
 	 unsigned bsp_apicid = 0;
 
+	 if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		 /* Nothing special needs to be done to find bus 0 */
+		 /* Allow the HT devices to be found */
 
+		 enumerate_ht_chain();
+		 bcm5785_enable_rom();
+		 bcm5785_enable_lpc();
+		 //enable RTC
+		pc87417_enable_dev(RTC_DEV);
+	 }
+
+
 	 if (bist == 0) {
 		 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	 }
Index: src/mainboard/tyan/s2912/romstage.c
===================================================================
--- src/mainboard/tyan/s2912/romstage.c	(revision 5251)
+++ src/mainboard/tyan/s2912/romstage.c	(working copy)
@@ -148,8 +148,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -176,78 +174,10 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the mcp55 */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -262,6 +192,18 @@ 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+	}
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	}
Index: src/mainboard/tyan/s2895/romstage.c
===================================================================
--- src/mainboard/tyan/s2895/romstage.c	(revision 5251)
+++ src/mainboard/tyan/s2895/romstage.c	(working copy)
@@ -116,8 +116,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -149,82 +147,10 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-	if (last_boot_normal_x) {
-	goto normal_image;
-	} else {
-	goto fallback_image;
-	}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-//	post_code(0x22);
-	if (bios_reset_detected() && last_boot_normal_x) {
-	goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-	goto normal_image;
-	}
-	else {
-	goto fallback_image;
-	}
- normal_image:
-//	post_code(0x23);
-	__asm__ volatile ("jmp __normal_image"
-	: /* outputs */
-	: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
-	);
-
- fallback_image:
-//	post_code(0x25);
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-	: /* outputs */
-	: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-	)
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	#if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-	#else
-	real_main(bist, cpu_init_detectedx);
-	#endif
-#else
-	#if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-	#endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -240,6 +166,18 @@ 
 	struct mem_controller ctrl[8];
 	unsigned nodes;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the ck804 */
+		ck804_enable_rom();
+	}
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 	}
Index: src/mainboard/tyan/s2895/failover.c (deleted)
===================================================================
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c	(revision 5251)
+++ src/mainboard/tyan/s2912_fam10/romstage.c	(working copy)
@@ -144,8 +144,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -170,81 +168,12 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	set_bsp_node_CHtExtNodeCfgEn();
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the mcp55 */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
@@ -253,6 +182,19 @@ 
 	u32 wants_reset;
 	msr_t msr;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+	}
+
 	post_code(0x30);
 
 	if (bist == 0) {
Index: src/mainboard/msi/ms7135/romstage.c
===================================================================
--- src/mainboard/msi/ms7135/romstage.c	(revision 5251)
+++ src/mainboard/msi/ms7135/romstage.c	(working copy)
@@ -100,9 +100,6 @@ 
 
 #endif	/* CONFIG_USE_FAILOVER_IMAGE */
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
-	|| ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -124,80 +121,9 @@ 
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
-
-	/* Is this a CPU only reset? Or is this a secondary CPU? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the BIOS? */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-
-	/* This is the primary CPU. How should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	} else {
-		goto fallback_image;
-	}
-
-normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		:					/* outputs */
-		:"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-		);
-
-fallback_image:
-
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-	__asm__ volatile ("jmp __fallback_image"
-		:					/* outputs */
-		:"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-		)
-#endif
-	;
-}
-
-#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-#if CONFIG_USE_FAILOVER_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#else
-	real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 		(0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
 		0, 0, 0, 0,
@@ -211,6 +137,17 @@ 
 	struct mem_controller ctrl[8];
 	unsigned nodes;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the ck804 */
+		ck804_enable_rom();
+	}
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 	}
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c	(revision 5251)
+++ src/mainboard/msi/ms9652_fam10/romstage.c	(working copy)
@@ -145,8 +145,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -165,81 +163,12 @@ 
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	set_bsp_node_CHtExtNodeCfgEn();
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the mcp55 */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
@@ -249,6 +178,19 @@ 
 	u32 wants_reset;
 	msr_t msr;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+	}
+
 	post_code(0x30);
 
 	if (bist == 0) {
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c	(revision 5251)
+++ src/mainboard/msi/ms7260/romstage.c	(working copy)
@@ -131,8 +131,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -154,75 +152,10 @@ 
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned int last_boot_normal_x = last_boot_normal();
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 
-	/* Is this a CPU only reset? Or is this a secondary CPU? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x)
-			goto normal_image;
-		else
-			goto fallback_image;
-	}
-
-	/* Nothing special needs to be done to find bus 0. */
-	/* Allow the HT devices to be found. */
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the MCP55. */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the BIOS? */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary CPU. How should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	} else {
-		goto fallback_image;
-	}
-
-normal_image:
-	__asm__ volatile ("jmp __normal_image":
-			  :"a" (bist), "b"(cpu_init_detectedx)
-	);
-
-fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image":
-			  :"a" (bist), "b"(cpu_init_detectedx)
-	)
-#endif
-	;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-#if CONFIG_USE_FAILOVER_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#else
-	real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
 		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
@@ -237,6 +170,17 @@ 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0. */
+		/* Allow the HT devices to be found. */
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the MCP55. */
+		mcp55_enable_rom();
+	}
+
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
Index: src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/romstage.c	(revision 5251)
+++ src/mainboard/nvidia/l1_2pvv/romstage.c	(working copy)
@@ -150,8 +150,6 @@ 
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -177,78 +175,9 @@ 
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
-
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the mcp55 */
-	mcp55_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		);
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-	__asm__ volatile ("jmp __fallback_image"
-		: /* outputs */
-		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-		)
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
+#if CONFIG_USE_FAILOVER_IMAGE==0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr [] = {
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
@@ -263,6 +192,18 @@ 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+	}
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	}
Index: src/mainboard/asus/a8n_e/romstage.c
===================================================================
--- src/mainboard/asus/a8n_e/romstage.c	(revision 5251)
+++ src/mainboard/asus/a8n_e/romstage.c	(working copy)
@@ -98,9 +98,6 @@ 
 
 #endif	/* CONFIG_USE_FAILOVER_IMAGE */
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
-	|| ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -121,80 +118,9 @@ 
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	unsigned last_boot_normal_x = last_boot_normal();
-
-	/* Is this a CPU only reset? Or is this a secondary CPU? */
-	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the BIOS? */
-	if (bios_reset_detected() && last_boot_normal_x) {
-		goto normal_image;
-	}
-
-	/* This is the primary CPU. How should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	} else {
-		goto fallback_image;
-	}
-
-normal_image:
-	__asm__ volatile ("jmp __normal_image"
-		:					/* outputs */
-		:"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-		);
-
-fallback_image:
-
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-	__asm__ volatile ("jmp __fallback_image"
-		:					/* outputs */
-		:"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-		)
-#endif
-	;
-}
-
-#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_HAVE_FAILOVER_BOOT == 1
-#if CONFIG_USE_FAILOVER_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#else
-	real_main(bist, cpu_init_detectedx);
-#endif
-#else
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);
-#endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
 	static const uint16_t spd_addr[] = {
 		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
 		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
@@ -208,6 +134,17 @@ 
 	unsigned nodes, bsp_apicid = 0;
 	struct mem_controller ctrl[8];
 
+	if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the ck804 */
+		ck804_enable_rom();
+	}
+
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx);