Patchwork Non-CBFS build infrastructure will disappear at some point

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Submitter Patrick Georgi
Date 2009-08-12 19:13:54
Message ID <4A831472.9060104@georgi-clan.de>
Download mbox | patch
Permalink /patch/116/
State Deferred
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Comments

Patrick Georgi - 2009-08-12 19:13:54
Hi,

attached patch removes much of the old style rom image layout. After
this patch, only CBFS is available.

It's
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

Before this patch, people should get some more time to adapt their local
trees, and there are a couple of boards that work better with some
changes to MTRR/XIP handling that I want to do before this patch.

Consider this post a warning that something with the effect of this
patch will end up in the repository eventually.


Patrick

Patch

Index: coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- coreboot-v2.orig/src/arch/i386/Config.lb
+++ coreboot-v2/src/arch/i386/Config.lb
@@ -1,46 +1,30 @@ 
-uses CONFIG_CBFS
 uses CONFIG_SMP
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_INIT
 uses CONFIG_HAVE_FAILOVER_BOOT
 uses CONFIG_USE_FAILOVER_IMAGE
 uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_CBFS
 
 init init/crt0.S.lb
 
-if CONFIG_CBFS
-	if CONFIG_USE_FAILOVER_IMAGE
-	else
-		initobject /src/lib/cbfs.o
-		initobject /src/console/vsprintf.o
-		initobject /src/lib/lzma.o
-	end
+if CONFIG_USE_FAILOVER_IMAGE
+else
+	initobject /src/lib/cbfs.o
+	initobject /src/console/vsprintf.o
+	initobject /src/lib/lzma.o
 end
 
 if CONFIG_HAVE_FAILOVER_BOOT
 	if CONFIG_USE_FAILOVER_IMAGE
 		ldscript init/ldscript_failover.lb
 	else
-		if CONFIG_CBFS
-			ldscript init/ldscript_cbfs.lb
-		else
-			ldscript init/ldscript.lb
-		end
+		ldscript init/ldscript_cbfs.lb
 	end
 else
-	if CONFIG_CBFS
-		if CONFIG_USE_FALLBACK_IMAGE
-			ldscript init/ldscript_fallback_cbfs.lb
-		else
-			ldscript init/ldscript_cbfs.lb
-		end
+	if CONFIG_USE_FALLBACK_IMAGE
+		ldscript init/ldscript_fallback_cbfs.lb
 	else
-		if CONFIG_USE_FALLBACK_IMAGE
-			ldscript init/ldscript_fallback.lb
-		else
-			ldscript init/ldscript.lb
-		end
+		ldscript init/ldscript_cbfs.lb
 	end
 end
 
@@ -83,13 +67,6 @@  end
 # catch the case where there is no compression
 makedefine PAYLOAD-1:=payload
 
-if CONFIG_CBFS
-else
-# match the case where a compression type is specified.
-makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_NRV2B):=payload.nrv2b
-makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_LZMA):=payload.lzma
-end
-
 # catch the case where there is precompression. Yes, this bites. 
 if CONFIG_PRECOMPRESSED_PAYLOAD 
 	makedefine PAYLOAD-1:=payload
@@ -106,8 +83,8 @@  if CONFIG_USE_FAILOVER_IMAGE
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
-		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
+		action "touch cbfs-support; ./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
+		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 ]; then echo l > cbfs-support; fi"
 	end
 end
 
Index: coreboot-v2/src/arch/i386/init/crt0.S.lb
===================================================================
--- coreboot-v2.orig/src/arch/i386/init/crt0.S.lb
+++ coreboot-v2/src/arch/i386/init/crt0.S.lb
@@ -74,19 +74,8 @@  __main:
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl %esi
-#if CONFIG_CBFS == 1
 	pushl $str_coreboot_ram_name
 	call cbfs_and_run_core
-#else
-	movl	$_liseg, %esi
-	movl	$_iseg,  %edi
-	movl	$_eiseg, %ecx
-	subl	%edi, %ecx
-	pushl %ecx
-	pushl %edi
-	pushl %esi
-	call copy_and_run_core
-#endif
 
 .Lhlt:	
 	intel_chip_post_macro(0xee)	/* post fe */
@@ -148,12 +137,10 @@  str_pre_main:        .string "Jumping to
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
 
-#if CONFIG_CBFS == 1
 # if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
 # else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
 # endif
-#endif
 
 #endif /* CONFIG_USE_DCACHE_RAM */
Index: coreboot-v2/src/arch/i386/lib/Config.lb
===================================================================
--- coreboot-v2.orig/src/arch/i386/lib/Config.lb
+++ coreboot-v2/src/arch/i386/lib/Config.lb
@@ -1,7 +1,6 @@ 
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_CBFS
 
 object c_start.S
 object cpu.c
@@ -15,9 +14,5 @@  initobject printk_init.o
 
 if CONFIG_USE_FAILOVER_IMAGE
 else
-	if CONFIG_CBFS
-		initobject cbfs_and_run.o
-	else
-		initobject copy_and_run.o
-	end
+	initobject cbfs_and_run.o
 end
Index: coreboot-v2/src/boot/Config.lb
===================================================================
--- coreboot-v2.orig/src/boot/Config.lb
+++ coreboot-v2/src/boot/Config.lb
@@ -1,9 +1,5 @@ 
 object hardwaremain.o
-if CONFIG_CBFS
-	object selfboot.o
-else
-	object elfboot.o
-end
+object selfboot.o
 if CONFIG_FS_PAYLOAD
 	object filo.o
 end
Index: coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- coreboot-v2.orig/src/boot/hardwaremain.c
+++ coreboot-v2/src/boot/hardwaremain.c
@@ -96,22 +96,11 @@  void hardwaremain(int boot_complete)
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
-#if CONFIG_CBFS == 1
 # if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_load_payload(lb_mem, "fallback/payload");
 # else
 	cbfs_load_payload(lb_mem, "normal/payload");
 # endif
-#else
-
-#if CONFIG_FS_PAYLOAD == 1
-#warning "CONFIG_FS_PAYLOAD is deprecated."
-	filo(lb_mem);
-#else
-#warning "elfboot will soon be deprecated."
-	elfboot(lb_mem);
-#endif
-#endif
 	printk(BIOS_ERR, "Boot failed.\n");
 }
 
Index: coreboot-v2/src/config/failovercalculation.lb
===================================================================
--- coreboot-v2.orig/src/config/failovercalculation.lb
+++ coreboot-v2/src/config/failovercalculation.lb
@@ -10,13 +10,8 @@  else
 	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
 	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
     else
-	if CONFIG_CBFS
-		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
-		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
-	else
-		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
-		default CONFIG_ROM_SECTION_OFFSET = 0
-	end
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
     end
 end
 
Index: coreboot-v2/src/config/nofailovercalculation.lb
===================================================================
--- coreboot-v2.orig/src/config/nofailovercalculation.lb
+++ coreboot-v2/src/config/nofailovercalculation.lb
@@ -6,13 +6,8 @@  if CONFIG_USE_FALLBACK_IMAGE
 	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
 	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
 else
-	if CONFIG_CBFS
-		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
-		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
-	else
-		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
-		default CONFIG_ROM_SECTION_OFFSET = 0
-	end
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
 end
 
 ##
Index: coreboot-v2/src/config/Options.lb
===================================================================
--- coreboot-v2.orig/src/config/Options.lb
+++ coreboot-v2/src/config/Options.lb
@@ -692,11 +692,6 @@  define CONFIG_FS_FAT
 	export always
 	comment "Enable FAT filesystem support"
 end
-define CONFIG_CBFS
-	default 1
-	export always
-	comment "The new CBFS file system"
-end
 define CONFIG_AUTOBOOT_DELAY
 	default 2
 	export always
Index: coreboot-v2/src/cpu/amd/car/copy_and_run.c
===================================================================
--- coreboot-v2.orig/src/cpu/amd/car/copy_and_run.c
+++ coreboot-v2/src/cpu/amd/car/copy_and_run.c
@@ -3,7 +3,6 @@ 
    2006/05/02 - stepan: move nrv2b to an extra file.
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(char*, unsigned ebp);
 
 static void copy_and_run(void)
@@ -26,38 +25,3 @@  static void copy_and_run_ap_code_in_car(
 # endif
 }
 #endif
-
-#else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(void)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	copy_and_run_core(src, dst, ilen, 0);
-}
-
-#if CONFIG_AP_CODE_IN_CAR == 1
-
-extern u8 _liseg_apc, _iseg_apc, _eiseg_apc;
-
-static void copy_and_run_ap_code_in_car(unsigned ret_addr)
-{
-        uint8_t *src, *dst;
-        unsigned long ilen;
-
-	src = &_liseg_apc;
-	dst = &_iseg_apc;
-	ilen = &_eiseg_apc - dst;
-
-	copy_and_run_core(src, dst, ilen, ret_addr);
-}
-#endif
-#endif
Index: coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
===================================================================
--- coreboot-v2.orig/src/cpu/amd/model_lx/cache_as_ram.inc
+++ coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -222,19 +222,8 @@  __main:
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl	%esi
-#if CONFIG_CBFS == 1
 	pushl $str_coreboot_ram_name
 	call cbfs_and_run_core
-#else
-	movl	$_liseg, %esi
-	movl	$_iseg,  %edi
-	movl	$_eiseg, %ecx
-	subl	%edi, %ecx
-	pushl	%ecx
-	pushl	%edi
-	pushl	%esi
-	call copy_and_run_core
-#endif
 
 .Lhlt:
 	intel_chip_post_macro(0xee)	/* post fail ee */
@@ -295,10 +284,8 @@  str_pre_main:        .string "Jumping to
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-#if CONFIG_CBFS == 1
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
-# else
+#else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
-# endif
 #endif
Index: coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- coreboot-v2.orig/src/cpu/x86/car/copy_and_run.c
+++ coreboot-v2/src/cpu/x86/car/copy_and_run.c
@@ -2,7 +2,6 @@ 
    (Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(char*, unsigned ebp);
 
 static void copy_and_run(unsigned cpu_reset)
@@ -17,25 +16,3 @@  static void copy_and_run(unsigned cpu_re
 # endif
 }
 
-#else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(unsigned cpu_reset)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	if (cpu_reset == 1) cpu_reset = -1;
-	else cpu_reset = 0;
-
-	copy_and_run_core(src, dst, ilen, cpu_reset);
-}
-#endif
-
Index: coreboot-v2/src/devices/pci_rom.c
===================================================================
--- coreboot-v2.orig/src/devices/pci_rom.c
+++ coreboot-v2/src/devices/pci_rom.c
@@ -35,17 +35,15 @@  struct rom_header * pci_rom_probe(struct
 	struct rom_header *rom_header;
 	struct pci_data *rom_data;
 
-	if (CONFIG_CBFS) {
-		void *v;
-		/* if it's in FLASH, then it's as if dev->on_mainboard was true */
-		v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
-		printk_debug("In cbfs, rom address for %s = %p\n", 
-				dev_path(dev), v);
-		if (v) {
-			dev->rom_address = (u32)v;
-			dev->on_mainboard = 1;
-		}
-	} 
+	void *v;
+	/* if it's in FLASH, then it's as if dev->on_mainboard was true */
+	v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
+	printk_debug("In cbfs, rom address for %s = %p\n",
+			dev_path(dev), v);
+	if (v) {
+		dev->rom_address = (u32)v;
+		dev->on_mainboard = 1;
+	}
 
 	if (dev->on_mainboard) {
 		/* this is here as a legacy path. We hope it goes away soon. Users should not have to 
Index: coreboot-v2/src/lib/Config.lb
===================================================================
--- coreboot-v2.orig/src/lib/Config.lb
+++ coreboot-v2/src/lib/Config.lb
@@ -25,11 +25,5 @@  initobject memset.o
 initobject memcpy.o
 initobject memcmp.o
 
-if CONFIG_CBFS
-	object cbfs.o
-	object lzma.o
-end
-
-if CONFIG_COMPRESSED_PAYLOAD_LZMA
-	object lzma.o
-end
+object cbfs.o
+object lzma.o
Index: coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/a-trend/atc-6220/Options.lb
+++ coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/a-trend/atc-6240/Options.lb
+++ coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/abit/be6-ii_v2_0/Options.lb
+++ coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -98,9 +97,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/advantech/pcm-5820/Options.lb
+++ coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/db800/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/db800/Options.lb
+++ coreboot-v2/src/mainboard/amd/db800/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/dbm690t/Options.lb
+++ coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -301,9 +300,4 @@  default CONFIG_GFXUMA=1
 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/norwich/Options.lb
+++ coreboot-v2/src/mainboard/amd/norwich/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/pistachio/Options.lb
+++ coreboot-v2/src/mainboard/amd/pistachio/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -301,9 +300,4 @@  default CONFIG_GFXUMA=1
 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/rumba/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/rumba/Options.lb
+++ coreboot-v2/src/mainboard/amd/rumba/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,10 +158,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -18,7 +18,6 @@ 
 #
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -362,9 +361,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -325,9 +324,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/arima/hdama/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/arima/hdama/Options.lb
+++ coreboot-v2/src/mainboard/arima/hdama/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -242,9 +241,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/artecgroup/dbe61/Options.lb
+++ coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asi/mb_5blgp/Options.lb
+++ coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asi/mb_5blmp/Options.lb
+++ coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_PIRQ_TABLE
-uses CONFIG_CBFS
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
 uses CONFIG_HAVE_HARD_RESET
@@ -162,9 +161,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=
 default CONFIG_VIDEO_MB = 0
 
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/a8n_e/Options.lb
+++ coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -167,9 +166,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/a8v-e_se/Options.lb
+++ coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
@@ -18,7 +18,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -167,9 +166,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/Options.lb
+++ coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
@@ -18,7 +18,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -176,9 +175,4 @@  default CONFIG_MAINBOARD_POWER_ON_AFTER_
 
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/mew-am/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/mew-am/Options.lb
+++ coreboot-v2/src/mainboard/asus/mew-am/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/mew-vm/Options.lb
+++ coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -158,9 +157,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 
 default CONFIG_UDELAY_TSC=1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/p2b-d/Options.lb
+++ coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,5 +102,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/p2b-ds/Options.lb
+++ coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,9 +103,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/p2b-f/Options.lb
+++ coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/p2b/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/p2b/Options.lb
+++ coreboot-v2/src/mainboard/asus/p2b/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -98,9 +97,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/p3b-f/Options.lb
+++ coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/axus/tc320/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/axus/tc320/Options.lb
+++ coreboot-v2/src/mainboard/axus/tc320/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/azza/pt-6ibd/Options.lb
+++ coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/bcom/winnet100/Options.lb
+++ coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/bcom/winnetp680/Options.lb
+++ coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,10 +102,4 @@  default HOSTCC = "gcc"
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/biostar/m6tba/Options.lb
+++ coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/broadcom/blast/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/broadcom/blast/Options.lb
+++ coreboot-v2/src/mainboard/broadcom/blast/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -260,9 +259,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
+++ coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/dell/s1850/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/dell/s1850/Options.lb
+++ coreboot-v2/src/mainboard/dell/s1850/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/digitallogic/adl855pc/Options.lb
+++ coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -113,11 +112,4 @@  default CONFIG_ROM_PAYLOAD     = 1
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c
===================================================================
--- coreboot-v2.orig/src/mainboard/digitallogic/msm586seg/mainboard.c
+++ coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c
@@ -35,9 +35,6 @@  static void irqdump()
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
 static void enable_dev(struct device *dev) {
-#if !CONFIG_CBFS
-	extern unsigned char *rom_start, *rom_end;
-#endif
 	volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
@@ -136,14 +133,6 @@  static void enable_dev(struct device *de
 	/* follow fuctory here */
 	mmcr->dmacontrol.extchanmapa = 0x3210;
 
-#if !CONFIG_CBFS
-	/* hack for IDIOTIC need to fix rom_start */
-	printk_err("Patching rom_start due to sc520 limits\n");
-	rom_start = 0x2000000 + 0x40000;
-	rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1;
-#endif
-
-	
 }
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
Index: coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/digitallogic/msm586seg/Options.lb
+++ coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -121,11 +120,4 @@  default CONFIG_ROM_PAYLOAD     = 1
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/digitallogic/msm800sev/Options.lb
+++ coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/eaglelion/5bcm/Options.lb
+++ coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -164,10 +163,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/embeddedplanet/ep405pc/Options.lb
+++ coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb
@@ -3,7 +3,6 @@ 
 ##
 
 uses CONFIG_PCIC0_CFGADDR 
-uses CONFIG_CBFS
 uses CONFIG_ARCH_X86
 uses CONFIG_PCIC0_CFGDATA 
 uses CONFIG_ISA_IO_BASE 
@@ -144,9 +143,4 @@  default CONFIG_ROMSTART=0xfff03000
 default CONFIG_RAMBASE=0x00100000
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/emulation/qemu-x86/Options.lb
+++ coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
@@ -48,13 +48,11 @@  uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CBFS
 
 
 default CONFIG_CONSOLE_SERIAL8250=1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-default CONFIG_CBFS=1
 
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE  = 256*1024
Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -22,7 +22,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/gigabyte/ga-6bxc/Options.lb
+++ coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Options.lb
+++ coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
@@ -20,7 +20,6 @@ 
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -359,10 +358,5 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 ### End Options.lb
 end
Index: coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/hp/dl145_g3/Options.lb
+++ coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
@@ -84,7 +84,6 @@  uses CONFIG_PCI_ROM_RUN
 uses CONFIG_HW_MEM_HOLE_SIZEK
 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_CBFS
 
 uses CONFIG_HT_CHAIN_UNITID_BASE
 uses CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -327,9 +326,5 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-##
-## CBFS
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end
Index: coreboot-v2/src/mainboard/ibm/e325/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/ibm/e325/Options.lb
+++ coreboot-v2/src/mainboard/ibm/e325/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -221,9 +220,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/ibm/e326/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/ibm/e326/Options.lb
+++ coreboot-v2/src/mainboard/ibm/e326/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -227,9 +226,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iei/juki-511p/Options.lb
+++ coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -145,10 +144,4 @@  default HOSTCC="gcc"
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iei/nova4899r/Options.lb
+++ coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -172,10 +171,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
+++ coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -106,10 +105,4 @@  default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/intel/eagleheights/Options.lb
+++ coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
@@ -70,7 +70,6 @@  uses CONFIG_HAVE_SMI_HANDLER
 uses CONFIG_PCIE_CONFIGSPACE_HOLE
 uses CONFIG_MMCONF_SUPPORT
 uses CONFIG_MMCONF_BASE_ADDRESS
-uses CONFIG_CBFS
 #
 uses CONFIG_MAINBOARD
 uses CONFIG_MAINBOARD_PART_NUMBER
@@ -322,10 +321,5 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end
Index: coreboot-v2/src/mainboard/intel/jarrell/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/intel/jarrell/Options.lb
+++ coreboot-v2/src/mainboard/intel/jarrell/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -242,9 +241,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/intel/mtarvon/Options.lb
+++ coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
@@ -18,7 +18,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -225,9 +224,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/intel/truxton/Options.lb
+++ coreboot-v2/src/mainboard/intel/truxton/Options.lb
@@ -18,7 +18,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -226,10 +225,4 @@  default CONFIG_MAINBOARD_POWER_ON_AFTER_
 
 ### End Options.lb
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/intel/xe7501devkit/Options.lb
+++ coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_HAVE_PIRQ_TABLE
@@ -240,9 +239,4 @@  default CONFIG_DEBUG=1
 # default CONFIG_CPU_OPT="-g"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Options.lb
+++ coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -326,9 +325,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iwill/dk8s2/Options.lb
+++ coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/iwill/dk8x/Options.lb
+++ coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -227,9 +226,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/jetway/j7f24/Options.lb
+++ coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,10 +103,4 @@  default HOSTCC = "gcc"
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/kontron/986lcd-m/Options.lb
+++ coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
@@ -71,7 +71,6 @@  uses CONFIG_PCIE_CONFIGSPACE_HOLE
 uses CONFIG_MMCONF_SUPPORT
 uses CONFIG_MMCONF_BASE_ADDRESS
 uses CONFIG_GFXUMA
-uses CONFIG_CBFS
 
 #
 uses CONFIG_MAINBOARD
@@ -327,10 +326,5 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-# 
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end
Index: coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/lippert/frontrunner/Options.lb
+++ coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,10 +158,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/lippert/roadrunner-lx/Options.lb
+++ coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
@@ -21,7 +21,6 @@ 
 ## Based on Options.lb from AMD's DB800 mainboard.
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -211,9 +210,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/lippert/spacerunner-lx/Options.lb
+++ coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
@@ -21,7 +21,6 @@ 
 ## Based on Options.lb from AMD's DB800 mainboard.
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -211,9 +210,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/mitac/6513wu/Options.lb
+++ coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
@@ -78,7 +77,6 @@  default CONFIG_ROM_IMAGE_SIZE = 128 * 10
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CBFS=1
 
 # RAM layout
 default CONFIG_RAMBASE = 0x00004000
Index: coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/motorola/sandpoint/Options.lb
+++ coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_SANDPOINT_ALTIMUS
-uses CONFIG_CBFS
 uses CONFIG_ARCH_X86
 uses CONFIG_SANDPOINT_TALUS
 uses CONFIG_SANDPOINT_UNITY
@@ -126,9 +125,4 @@  default CONFIG_RAMSTART=0x00100000
 default CONFIG_SANDPOINT_ALTIMUS=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
+++ coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
@@ -1,6 +1,5 @@ 
 uses CONFIG_ARCH_X86
 uses CONFIG_ISA_IO_BASE
-uses CONFIG_CBFS
 uses CONFIG_ISA_MEM_BASE
 uses CONFIG_PCIC0_CFGADDR
 uses CONFIG_PCIC0_CFGDATA
@@ -121,9 +120,4 @@  default CONFIG_RAMBASE=0x00100000
 default CONFIG_RAMSTART=0x00100000
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms6119/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms6119/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms6119/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms6147/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms6147/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms6147/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms6178/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms6178/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms6178/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,7 +96,6 @@  default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS = 1
 default CONFIG_HAVE_HIGH_TABLES = 1
 default CONFIG_VIDEO_MB = 1
 end
Index: coreboot-v2/src/mainboard/msi/ms7135/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms7135/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms7135/Options.lb
@@ -21,7 +21,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -320,9 +319,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms7260/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms7260/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms7260/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -186,9 +185,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms9185/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms9185/Options.lb
@@ -23,7 +23,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -327,9 +326,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/msi/ms9282/Options.lb
+++ coreboot-v2/src/mainboard/msi/ms9282/Options.lb
@@ -23,7 +23,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -307,9 +306,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/nec/powermate2000/Options.lb
+++ coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -96,9 +95,4 @@  default CONFIG_TSC_X86RDTSC_CALIBRATE_WI
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/newisys/khepri/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/newisys/khepri/Options.lb
+++ coreboot-v2/src/mainboard/newisys/khepri/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -243,9 +242,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -349,9 +348,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/olpc/btest/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/olpc/btest/Options.lb
+++ coreboot-v2/src/mainboard/olpc/btest/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,11 +158,3 @@  default CONFIG_TTYS0_LCS=0x3
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-end
Index: coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/olpc/rev_a/Options.lb
+++ coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,11 +158,3 @@  default CONFIG_TTYS0_LCS=0x3
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-end
Index: coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/pcengines/alix1c/Options.lb
+++ coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -198,10 +197,4 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/rca/rm4100/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/rca/rm4100/Options.lb
+++ coreboot-v2/src/mainboard/rca/rm4100/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
@@ -96,9 +95,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_VENDOR = "RCA"
 default CONFIG_MAINBOARD_PART_NUMBER = "RM4100"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
+++ coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -96,5 +95,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/sunw/ultra40/Options.lb
+++ coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -276,9 +275,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
@@ -20,7 +20,6 @@ 
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
@@ -20,7 +20,6 @@ 
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -348,11 +347,5 @@  default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end
Index: coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/x6dai_g/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/x6dhe_g/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/x6dhe_g2/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/x6dhr_ig/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/supermicro/x6dhr_ig2/Options.lb
+++ coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@  default  CONFIG_CONSOLE_BTEXT=0
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/technexion/tim8690/Options.lb
+++ coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
Index: coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c
===================================================================
--- coreboot-v2.orig/src/mainboard/technologic/ts5300/mainboard.c
+++ coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c
@@ -35,9 +35,6 @@  static void irqdump()
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
 static void enable_dev(struct device *dev) {
-#if !CONFIG_CBFS
-	extern unsigned char *rom_start, *rom_end;
-#endif
 	volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
@@ -141,13 +138,6 @@  static void enable_dev(struct device *de
 	mmcr->dmacontrol.extchanmapa = 0xf210;
 	mmcr->dmacontrol.extchanmapb = 0xffff;
 
-#if !CONFIG_CBFS
-	/* hack for IDIOTIC need to fix rom_start */
-	printk_err("Patching rom_start due to sc520 limits\n");
-	rom_start = 0x09400000 + 0xe0000;
-	rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1;
-#endif
-
 	printk_err("TS5300 EXIT %s\n", __func__);
 	
 }
Index: coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/technologic/ts5300/Options.lb
+++ coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -136,9 +135,4 @@  default CONFIG_ROM_PAYLOAD     = 1
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/televideo/tc7020/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/televideo/tc7020/Options.lb
+++ coreboot-v2/src/mainboard/televideo/tc7020/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,9 +103,4 @@  default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/thomson/ip1000/Options.lb
+++ coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
@@ -96,9 +95,4 @@  default CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_VENDOR = "THOMSON"
 default CONFIG_MAINBOARD_PART_NUMBER = "IP1000"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/totalimpact/briq/Options.lb
+++ coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
@@ -3,7 +3,6 @@ 
 ##
 
 uses CONFIG_TTYS0_DIV
-uses CONFIG_CBFS
 uses CONFIG_ARCH_X86
 uses CONFIG_TTYS0_BASE
 uses CONFIG_BRIQ_750FX
@@ -128,9 +127,4 @@  default CONFIG_BRIQ_750FX=1
 #default CONFIG_BRIQ_7400=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s1846/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s1846/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s1846/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -98,9 +97,4 @@  default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2735/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2735/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2735/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -256,9 +255,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2850/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2850/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2850/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2875/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2875/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2875/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -245,9 +244,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2880/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2880/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2880/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2881/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2881/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2881/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -261,9 +260,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2882/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2882/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2882/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2885/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2885/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2885/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -271,9 +270,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2891/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2891/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2891/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -300,9 +299,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2892/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2892/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2892/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -288,9 +287,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2895/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2895/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2895/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -307,9 +306,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2912_fam10/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -360,9 +359,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s2912/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s2912/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s2912/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s4880/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s4880/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s4880/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -253,9 +252,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/tyan/s4882/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/tyan/s4882/Options.lb
+++ coreboot-v2/src/mainboard/tyan/s4882/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -252,9 +251,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/epia-cn/Options.lb
+++ coreboot-v2/src/mainboard/via/epia-cn/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,10 +103,4 @@  default HOSTCC = "gcc"
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/epia-m/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/epia-m/Options.lb
+++ coreboot-v2/src/mainboard/via/epia-m/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -143,10 +142,4 @@  default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default  CONFIG_CONSOLE_SERIAL8250=1
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/epia-m700/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/epia-m700/Options.lb
+++ coreboot-v2/src/mainboard/via/epia-m700/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -137,7 +136,6 @@  default CC = "$(CONFIG_CROSS_COMPILE)gcc
 default HOSTCC = "gcc"
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CBFS=1
 
 ##
 ## Set this to the max PCI bus number you would ever use for PCI config I/O.
Index: coreboot-v2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/epia-n/Options.lb
+++ coreboot-v2/src/mainboard/via/epia-n/Options.lb
@@ -20,7 +20,6 @@ 
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_FAILOVER_BOOT
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -118,10 +117,4 @@  default HOSTCC = "gcc"
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/epia/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/epia/Options.lb
+++ coreboot-v2/src/mainboard/via/epia/Options.lb
@@ -1,5 +1,4 @@ 
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CBFS
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_TTYS0_BAUD
@@ -141,10 +140,4 @@  default CC="$(CONFIG_CROSS_COMPILE)gcc -
 default HOSTCC="gcc"
 
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/pc2500e/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/pc2500e/Options.lb
+++ coreboot-v2/src/mainboard/via/pc2500e/Options.lb
@@ -19,7 +19,6 @@ 
 ##
 
 uses CONFIG_SMP
-uses CONFIG_CBFS
 uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
@@ -112,10 +111,4 @@  default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end
Index: coreboot-v2/src/mainboard/via/vt8454c/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/via/vt8454c/Options.lb
+++ coreboot-v2/src/mainboard/via/vt8454c/Options.lb
@@ -55,7 +55,6 @@  uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CBFS
 
 # compiler specifics
 uses CONFIG_CROSS_COMPILE
@@ -243,10 +242,5 @@  default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
 
-#
-# CBFS
-# 
-default CONFIG_CBFS=1
-
 end
 
Index: coreboot-v2/util/abuild/abuild
===================================================================
--- coreboot-v2.orig/util/abuild/abuild
+++ coreboot-v2/util/abuild/abuild
@@ -176,20 +176,12 @@  EOF
 			cat <<EOF
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-if CONFIG_CBFS
-else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-end
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-if CONFIG_CBFS
-else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-end
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: coreboot-v2/util/newconfig/config.g
===================================================================
--- coreboot-v2.orig/util/newconfig/config.g
+++ coreboot-v2/util/newconfig/config.g
@@ -2247,9 +2247,6 @@  def writemakefile(path):
 	file = safe_open(makefilepath, 'w+')
 	writemakefileheader(file, makefilepath)
 
-	# Hack to get the necessary settings (CONFIG_CBFS):
-	file.write("include %s/Makefile.settings\n\n" % romimages.keys()[0])
-
 	# main rule
 	file.write("\nall: ")
 	for i in buildroms:
@@ -2275,9 +2272,8 @@  def writemakefile(path):
 	file.write("base-clean:\n")
 	file.write("\trm -f romcc*\n\n")
 
-	file.write("ifeq \"$(CONFIG_CBFS)\" \"1\"\n\n")
 	file.write("CBFS_COMPRESS_FLAG:=\n")
-	file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\nendif\n\n")
+	file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\n\n")
 
 	for i in buildroms:
 		file.write("%s: cbfstool" %(i.name))
Index: coreboot-v2/NEWS
===================================================================
--- coreboot-v2.orig/NEWS
+++ coreboot-v2/NEWS
@@ -1,68 +1,12 @@ 
-- 2.0.0
-  - this NEWS file is neglected in favor of the svn commit logs.
-    See http://tracker.coreboot.org/
-- 1.1.8
-  - Store everything in arch
-- 1.1.7
-  - The configuration language has been cleaned up.  No more link keyword.
-  - Everything is now in the device tree.
-  - The static and dynamic device trees have been unified
-  - Support for setting the pci subsystem vendor and pci subsystem device has been added.
-  - 64bit resource support
-  - Generic smbus support
-- 1.1.6
-  - pnp/superio devices are now handled cleanly with very little code
-  - Initial support for finding x86 BIST errors
-  - static resource assignments can now be specified in Config.lb
-  - special VGA I/O decode now should work
-  - added generic PCI error reporting enables
-  - build_opt_tbl now generates a header that allows cmos settings to
-    be read from romcc compiled code.
-  - split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED
-  - romcc now gracesfully handles function pointers instead of dying mysteriously
-  - First regression test in amdk8/raminit_test
-- 1.1.5
-  - O2, enums, and switch statements work in romcc
-  - Support for compiling romcc on non x86 platforms
-  - new romc options -msse and -mmmx for specifying extra registers to use
-  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
-  - Move the link specification to the chip specification instead of the path
-  - Allow specifying devices with internal bridges.
-  - Initial via epia support
-  - Opteron errata fixes
-- 1.1.4
-  Major restructuring of hypertransport handling.
-  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
-  Updates to hard_reset handling when resetting because of the need to change hypertransport link
-    speeds and widths. 
-    (a) No longer assume the boot is good just because we get to a hard reset point.
-    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
-        boot counter.
-  Updates to arima/hdama mptable so it tracks the new bus numbers
-- 1.1.3
-  Major update of the dyanmic device tree to so it can handle
-  * subtractive resources
-  * merging with the static device tree
-  * more device types than just pci
-- 1.1.2
-  Add back in the hard_reset method from freebios1 this allows generic
-  code to reset the box.  
-  Update the hypertransport setup code to automatically optimize
-  hypertransport link widths and frequencies, and to call hard_reset
-  if necessary for the changes to go into effect.
-- 1.1.1
-  Updates to the new configuration system so it works more reliably
-  Removed a bunch of unused configuration variables
-  Removed a bunch of unused assembly code
-- 1.1.0
-  A whole bunch of random ppc and opteron work we never put a good label on
-- 1.1.0
-Intial development release of LinuxBIOS.
-Everything is thrown overboard and will be reincluded as necessary so we can
-get rid of the legacy baggage.  Since LinuxBIOS was started we have developed
-some better techniques for some things, but we still hang on to the old ways
-because some ports that we want not to break depend on them.  So we preserve
-them by preserve the 1.0.x series and keeping only the best practices for
-the 1.1.x series.  When there is a stable port this code base will
-become LinuxBIOS 2.0.x and the core will become frozen.
+coreboot version 2.1 - 2009-mm-dd
+---------------------------------
+This version features the removal of the old style ROM image layout in favor of
+CBFS. CONFIG_CBFS was removed as there is no way to unselect it.
 
+Issues:
+- cpu/amd/model_lx contains some untested changes in the coreboot_ram
+  loading stage
+- The coreboot_ram loader sets up its own stack at 0x4000000. This has two
+  implications:
+  1. This memory should probably stay alive (eg. resume from suspend)
+  2. There might be collisions on SMP (eg. when loading coreboot_apc)