Patchwork refactor crt0.S.lb

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Submitter Patrick Georgi
Date 2010-04-08 20:17:11
Message ID <4BBE39C7.6060304@georgi-clan.de>
Download mbox | patch
Permalink /patch/1206/
State Accepted
Headers show

Comments

Patrick Georgi - 2010-04-08 20:17:11
(retry, the first attempt seems to have been eaten by the list daemon)

Hi,

attached patch splits crt0.S.lb, adds the first part of it as first
element of crt0s, adds the second part as last element of crt0s on romcc
boards (it was guarded with #if CONFIG_USE_DCACHE_RAM==0), renames
crt0_includes.h to crt0.S and runs this, instead of crt0.S.lb through
the assembler.

Minor clean up, but I hope it's clearer what's loaded when with this change.

It passes abuild.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Stefan Reinauer - 2010-04-08 20:28:10
Acked-by: Stefan Reinauer <stepan@coresystems.de>

On 4/8/10 10:17 PM, Patrick Georgi wrote:
> (retry, the first attempt seems to have been eaten by the list daemon)
>
> Hi,
>
> attached patch splits crt0.S.lb, adds the first part of it as first
> element of crt0s, adds the second part as last element of crt0s on romcc
> boards (it was guarded with #if CONFIG_USE_DCACHE_RAM==0), renames
> crt0_includes.h to crt0.S and runs this, instead of crt0.S.lb through
> the assembler.
>
> Minor clean up, but I hope it's clearer what's loaded when with this change.
>
> It passes abuild.
>
> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
>
>

Patch

Index: src/arch/i386/Makefile.bootblock.inc
===================================================================
--- src/arch/i386/Makefile.bootblock.inc	(revision 5378)
+++ src/arch/i386/Makefile.bootblock.inc	(working copy)
@@ -96,7 +96,7 @@ 
 	mkdir -p $(obj)/romstage
 	printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@
 
-$(obj)/romstage/crt0_includes.h: $$(crt0s)
+$(obj)/romstage/crt0.S: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	mkdir -p $(obj)/romstage
 	printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
@@ -105,7 +105,7 @@ 
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
 
Index: src/arch/i386/init/crt0.S.lb
===================================================================
--- src/arch/i386/init/crt0.S.lb	(revision 5378)
+++ src/arch/i386/init/crt0.S.lb	(working copy)
@@ -1,147 +0,0 @@ 
-/* -*- asm -*-
- * $ $
- *
- */
-
-/* 
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
- *
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
- *
- * - Converted to gas assembly, and refitted to work with etherboot.
- *   Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- *   Eric Biederman 26 Sept 2002
- */
-
-
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>	
-
-#ifndef ASM_CONSOLE_LOGLEVEL
-#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-#endif
-
-/*
- * This is the entry code the code in .reset section
- * jumps to this address.
- *
- */
-.section ".rom.data", "a", @progbits
-.section ".rom.text", "ax", @progbits
-
-	post_code(0x01)             /* delay for chipsets */
-
-#include "crt0_includes.h"
-
-#if CONFIG_USE_DCACHE_RAM == 0
-#ifndef CONSOLE_DEBUG_TX_STRING
-	/* uses:	 esp, ebx, ax, dx */
-# define __CRT_CONSOLE_TX_STRING(string) \
-	mov	string, %ebx	; \
-	CALLSP(crt_console_tx_string)
-
-# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-#  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
-# else
-#  define CONSOLE_DEBUG_TX_STRING(string)
-# endif
-#endif
-
-	/* clear boot_complete flag */
-	xorl	%ebp, %ebp
-__main:
-	CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
-
-	/*
-	 *	Copy data into RAM and clear the BSS. Since these segments
-	 *	isn\'t really that big we just copy/clear using bytes, not
-	 *	double words.
-	 */
-	post_code(0x11)		/* post 11 */
-
-	cld				/* clear direction flag */
-	
-	/* copy coreboot from it's initial load location to 
-	 * the location it is compiled to run at.
-	 * Normally this is copying from FLASH ROM to RAM.
-	 */
-	movl	%ebp, %esi
-	/* FIXME: look for a proper place for the stack */
-	movl	$0x4000000, %esp
-	movl	%esp, %ebp
-	pushl %esi
-	pushl $str_coreboot_ram_name
-	call cbfs_and_run_core
-
-.Lhlt:	
-	post_code(0xee)	/* post fe */
-	hlt
-	jmp	.Lhlt
-
-#ifdef __CRT_CONSOLE_TX_STRING
-	/* Uses esp, ebx, ax, dx  */
-crt_console_tx_string:
-	mov	(%ebx), %al
-	inc	%ebx
-	cmp	$0, %al
-	jne	9f
-	RETSP
-9:
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE	0x3f8
-#endif
-/* Data */
-#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
-
-/* Control */
-#define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
-#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
-#define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
-#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
-#define TTYS0_DLL TTYS0_RBR
-#define TTYS0_DLM TTYS0_IER
-
-/* Status */
-#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
-#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
-#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
-	
-	mov	%al, %ah
-10:	mov	$TTYS0_LSR, %dx
-	inb	%dx, %al
-	test	$0x20, %al
-	je	10b
-	mov	$TTYS0_TBR, %dx
-	mov	%ah, %al
-	outb	%al, %dx
-
-	jmp crt_console_tx_string
-#endif /* __CRT_CONSOLE_TX_STRING */
-
-#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-.section ".rom.data"
-#if CONFIG_COMPRESS
-str_copying_to_ram:  .string "Uncompressing coreboot to RAM.\r\n"
-#else
-str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
-#endif
-str_pre_main:        .string "Jumping to coreboot.\r\n"
-.previous
-
-#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-
-str_coreboot_ram_name:	.ascii CONFIG_CBFS_PREFIX
-			.string "/coreboot_ram"
-
-#endif /* CONFIG_USE_DCACHE_RAM */
Index: src/arch/i386/init/crt0_prologue.inc
===================================================================
--- src/arch/i386/init/crt0_prologue.inc	(revision 5378)
+++ src/arch/i386/init/crt0_prologue.inc	(working copy)
@@ -1,23 +1,10 @@ 
-/* -*- asm -*-
- * $ $
- *
- */
-
 /* 
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+ * Copyright 2002 Eric Biederman
  *
  * This file is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
- *
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
- *
- * - Converted to gas assembly, and refitted to work with etherboot.
- *   Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- *   Eric Biederman 26 Sept 2002
  */
 
 
@@ -39,109 +26,3 @@ 
 
 	post_code(0x01)             /* delay for chipsets */
 
-#include "crt0_includes.h"
-
-#if CONFIG_USE_DCACHE_RAM == 0
-#ifndef CONSOLE_DEBUG_TX_STRING
-	/* uses:	 esp, ebx, ax, dx */
-# define __CRT_CONSOLE_TX_STRING(string) \
-	mov	string, %ebx	; \
-	CALLSP(crt_console_tx_string)
-
-# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-#  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
-# else
-#  define CONSOLE_DEBUG_TX_STRING(string)
-# endif
-#endif
-
-	/* clear boot_complete flag */
-	xorl	%ebp, %ebp
-__main:
-	CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
-
-	/*
-	 *	Copy data into RAM and clear the BSS. Since these segments
-	 *	isn\'t really that big we just copy/clear using bytes, not
-	 *	double words.
-	 */
-	post_code(0x11)		/* post 11 */
-
-	cld				/* clear direction flag */
-	
-	/* copy coreboot from it's initial load location to 
-	 * the location it is compiled to run at.
-	 * Normally this is copying from FLASH ROM to RAM.
-	 */
-	movl	%ebp, %esi
-	/* FIXME: look for a proper place for the stack */
-	movl	$0x4000000, %esp
-	movl	%esp, %ebp
-	pushl %esi
-	pushl $str_coreboot_ram_name
-	call cbfs_and_run_core
-
-.Lhlt:	
-	post_code(0xee)	/* post fe */
-	hlt
-	jmp	.Lhlt
-
-#ifdef __CRT_CONSOLE_TX_STRING
-	/* Uses esp, ebx, ax, dx  */
-crt_console_tx_string:
-	mov	(%ebx), %al
-	inc	%ebx
-	cmp	$0, %al
-	jne	9f
-	RETSP
-9:
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE	0x3f8
-#endif
-/* Data */
-#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
-
-/* Control */
-#define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
-#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
-#define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
-#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
-#define TTYS0_DLL TTYS0_RBR
-#define TTYS0_DLM TTYS0_IER
-
-/* Status */
-#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
-#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
-#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
-	
-	mov	%al, %ah
-10:	mov	$TTYS0_LSR, %dx
-	inb	%dx, %al
-	test	$0x20, %al
-	je	10b
-	mov	$TTYS0_TBR, %dx
-	mov	%ah, %al
-	outb	%al, %dx
-
-	jmp crt_console_tx_string
-#endif /* __CRT_CONSOLE_TX_STRING */
-
-#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-.section ".rom.data"
-#if CONFIG_COMPRESS
-str_copying_to_ram:  .string "Uncompressing coreboot to RAM.\r\n"
-#else
-str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
-#endif
-str_pre_main:        .string "Jumping to coreboot.\r\n"
-.previous
-
-#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-
-str_coreboot_ram_name:	.ascii CONFIG_CBFS_PREFIX
-			.string "/coreboot_ram"
-
-#endif /* CONFIG_USE_DCACHE_RAM */
Index: src/arch/i386/init/crt0_romcc_epilogue.inc
===================================================================
--- src/arch/i386/init/crt0_romcc_epilogue.inc	(revision 5378)
+++ src/arch/i386/init/crt0_romcc_epilogue.inc	(working copy)
@@ -21,27 +21,6 @@ 
  */
 
 
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>	
-
-#ifndef ASM_CONSOLE_LOGLEVEL
-#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-#endif
-
-/*
- * This is the entry code the code in .reset section
- * jumps to this address.
- *
- */
-.section ".rom.data", "a", @progbits
-.section ".rom.text", "ax", @progbits
-
-	post_code(0x01)             /* delay for chipsets */
-
-#include "crt0_includes.h"
-
-#if CONFIG_USE_DCACHE_RAM == 0
 #ifndef CONSOLE_DEBUG_TX_STRING
 	/* uses:	 esp, ebx, ax, dx */
 # define __CRT_CONSOLE_TX_STRING(string) \
@@ -143,5 +122,3 @@ 
 
 str_coreboot_ram_name:	.ascii CONFIG_CBFS_PREFIX
 			.string "/coreboot_ram"
-
-#endif /* CONFIG_USE_DCACHE_RAM */
Index: src/arch/i386/Makefile.bigbootblock.inc
===================================================================
--- src/arch/i386/Makefile.bigbootblock.inc	(revision 5378)
+++ src/arch/i386/Makefile.bigbootblock.inc	(working copy)
@@ -16,7 +16,7 @@ 
 	printf 'INCLUDE "ldoptions"\n' > $@
 	printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@
 
-$(obj)/crt0_includes.h: $$(crt0s)
+$(obj)/crt0.S: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
 
@@ -24,7 +24,7 @@ 
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
 
Index: src/arch/i386/Makefile.inc
===================================================================
--- src/arch/i386/Makefile.inc	(revision 5378)
+++ src/arch/i386/Makefile.inc	(working copy)
@@ -100,7 +100,7 @@ 
 #######################################################################
 # done
 
-crt0s =
+crt0s = $(src)/arch/i386/init/crt0_prologue.inc
 ldscripts =
 ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
@@ -196,6 +196,10 @@ 
 ldscripts += $(chipset_bootblock_lds)
 endif
 
+ifeq ($(CONFIG_ROMCC),y)
+crt0s += $(src)/arch/i386/init/crt0_romcc_epilogue.inc
+endif
+
 OPTION_TABLE_H:=
 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
 OPTION_TABLE_H:=$(obj)/option_table.h
Index: Makefile
===================================================================
--- Makefile	(revision 5378)
+++ Makefile	(working copy)
@@ -320,7 +320,7 @@ 
 	rm -f $(DEPENDENCIES)
 	rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
 	rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.*
-	rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript
+	rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
 	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
 	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
 	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc