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Submitter marc bertens
Date 2010-04-10 11:33:43
Message ID <1270899223.12177.20.camel@andrala.reboot>
Download mbox | patch
Permalink /patch/1215/
State Superseded
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marc bertens - 2010-04-10 11:33:43
Hi all,

Here is my svn diff for the Nokia IP530, currently its able to run
coreboot + seabios + sgabios. 

The following hardware works;
	P3
	i440BX	northbridge
	82371	southbridge
	IDE	normal disks + CF
	
The following hardware does'nt work:
	4x NIC 		21143-PD
	2x PCMCIA 	PCI1225PDV

For flashing the the bios you need the following patches from patchwork
	http://patchwork.coreboot.org/patch/1185/
		Intel 28F004/28F400 support
	http://patchwork.coreboot.org/patch/1195/
		[v2,compilable] Board enable for IP530 


I will work on the remaining issues, when someone has any good ideas to
tackle the remainder issues that will  be apriciated.



Marc
Uwe Hermann - 2010-04-11 21:21:24
On Sat, Apr 10, 2010 at 01:33:43PM +0200, Marc Bertens wrote:
> Hi all,
> 
> Here is my svn diff for the Nokia IP530, currently its able to run
> coreboot + seabios + sgabios. 

Thanks! Please post your Signed-off-by for all patches you send, so we
can commit them.

http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure


> Index: src/mainboard/Kconfig
> ===================================================================
> --- src/mainboard/Kconfig	(revision 5355)
> +++ src/mainboard/Kconfig	(working copy)
> @@ -96,6 +96,8 @@
>  	bool "VIA"
>  config VENDOR_WINENT
>  	bool "Win Enterprises"
> +config VENDOR_NOKIA
> +	bool "Nokia"
>  
>  endchoice
>  
> @@ -359,6 +361,11 @@
>  	default "Win Enterprise"
>  	depends on VENDOR_WINENT
>  
> +config MAINBOARD_VENDOR
> +	string
> +	default "Nokia"
> +	depends on VENDOR_NOKIA
> +
>  source "src/mainboard/a-trend/Kconfig"
>  source "src/mainboard/abit/Kconfig"
>  source "src/mainboard/advantech/Kconfig"
> @@ -405,6 +412,7 @@
>  source "src/mainboard/tyan/Kconfig"
>  source "src/mainboard/via/Kconfig"
>  source "src/mainboard/winent/Kconfig"
> +source "src/mainboard/nokia/Kconfig"

Please insert the above entries in alphabetical order respectively
(not as last entries in the lists).

 
> Index: src/mainboard/nokia/Kconfig
> ===================================================================
> --- src/mainboard/nokia/Kconfig	(revision 0)
> +++ src/mainboard/nokia/Kconfig	(revision 0)
> @@ -0,0 +1,29 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +choice
> +	prompt "Mainboard model"
> +	depends on VENDOR_NOKIA


> +##source "src/mainboard/nokia/ip330/Kconfig"

This can be dropped, I assume?


> +source "src/mainboard/nokia/ip530/Kconfig"
> +
> +endchoice
> +
> Index: src/mainboard/nokia/ip530/Kconfig
> ===================================================================
> --- src/mainboard/nokia/ip530/Kconfig	(revision 0)
> +++ src/mainboard/nokia/ip530/Kconfig	(revision 0)
> @@ -0,0 +1,54 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +config BOARD_NOKIA_IP530
> +	bool "IP530"
> +	select ARCH_X86
> +##	select CPU_INTEL_SLOT_1
> +	select CPU_INTEL_SOCKET_PGA370

Is this correct? If it's 440BX chipset it's very likely to be Slot 1.


> +	select NORTHBRIDGE_INTEL_I440BX
> +	select SOUTHBRIDGE_INTEL_I82371EB

> +##	select SUPERIO_WINBOND_W83977TF
> +	select SUPERIO_SMSC_SMSCSUPERIO

This also looks strange. Which Super I/O is actually on the board?


> Index: src/mainboard/nokia/ip530/devicetree.cb
> ===================================================================
> --- src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
> +++ src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
> @@ -0,0 +1,81 @@

Please add the missing license header to this file.


> +chip northbridge/intel/i440bx		# Northbridge
> +  device apic_cluster 0 on		# APIC cluster
> +    chip cpu/intel/socket_PGA370		# CPU

Slot 1? See above.


> +      device pci 7.2 on	end		# USB
> +      device pci 7.3 on end		# ACPI
> +      register "ide0_enable" = "1"
> +      register "ide1_enable" = "1"
> +      register "ide_legacy_enable" = "1"
> +      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
> +      register "ide0_drive0_udma33_enable" = "0"
> +      register "ide0_drive1_udma33_enable" = "0"
> +      register "ide1_drive0_udma33_enable" = "0"
> +      register "ide1_drive1_udma33_enable" = "0"

I think you can safely set these to "1" too. Actually, we should do this
for all 440BX boards IMHO (per default). If any user should have issues
it's easy enough to set to "0".


> +    end
> +    device pci 0d.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> +    end
> +    device pci 0e.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> +    end
> +    device pci 0f.0 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
> +    end
> +    device pci 0f.1 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
> +    end
> +  end


> +  device pci_domain 1 on		# PCI domain 01
> +    device pci 00.0 on 		# PCI bridge: Digital Equipment Corporation DECchip 21150 (rev 06) (prog-if 00 [Normal decode])
> +    end
> +  end
> +  device pci_domain 2 on		# PCI domain 02
> +    device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> +    end
> +    device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> +    end
> +  end

Not sure if this is needed?

Have you posted "lspci -tvnn" of your board somewhere?


> Index: src/mainboard/nokia/ip530/asus_p2b_irq_tables.c
> ===================================================================
> --- src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)
> +++ src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)

This must be renamed to irq_tables.c of course. If it does not fully work
yet, we can either commit it if it partially works, or drop it completely
for now.


> Index: src/mainboard/nokia/ip530/irq_tables.c
> ===================================================================
> --- src/mainboard/nokia/ip530/irq_tables.c	(revision 0)
> +++ src/mainboard/nokia/ip530/irq_tables.c	(revision 0)

Oh, there's an irq_tables.c already, so the above can be dropped I guess.


> @@ -0,0 +1,53 @@
> +const struct irq_routing_table intel_irq_routing_table = {
> +	PIRQ_SIGNATURE,		/* u32 signature */
> +	PIRQ_VERSION,		/* u16 version */
> +	32 + 16 * 6,		/* Max. number of devices on the bus */

Replace 6 with IRQ_SLOT_COUNT here.


Uwe.
marc bertens - 2010-04-12 04:32:16
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>

Op zaterdag 10-04-2010 om 13:33 uur [tijdzone +0200], schreef Marc
Bertens:
> Hi all,
> 
> Here is my svn diff for the Nokia IP530, currently its able to run
> coreboot + seabios + sgabios. 
> 
> The following hardware works;
> 	P3
> 	i440BX	northbridge
> 	82371	southbridge
> 	IDE	normal disks + CF
> 	
> The following hardware does'nt work:
> 	4x NIC 		21143-PD
> 	2x PCMCIA 	PCI1225PDV
> 
> For flashing the the bios you need the following patches from patchwork
> 	http://patchwork.coreboot.org/patch/1185/
> 		Intel 28F004/28F400 support
> 	http://patchwork.coreboot.org/patch/1195/
> 		[v2,compilable] Board enable for IP530 
> 
> 
> I will work on the remaining issues, when someone has any good ideas to
> tackle the remainder issues that will  be apriciated.
> 
> 
> 
> Marc 
> 
> 		  
>
Uwe Hermann - 2010-04-19 21:34:12
On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
> Signed-off-by: Marc Bertens <mbertens@xs4all.nl>

Thanks, committed in r5458 with some of the changes I mentioned.
Sorry for the delay.

Can you please post lspci -tvnn and some more status info? I'd like
to add a wiki page for the board, similar to this one:

http://www.coreboot.org/ASUS_P2B


Thanks, Uwe.
Stefan Reinauer - 2010-04-19 22:34:32
On 4/19/10 11:34 PM, Uwe Hermann wrote:
> On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
>   
>> Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
>>     
> Thanks, committed in r5458 with some of the changes I mentioned.
> Sorry for the delay.
>
> Can you please post lspci -tvnn and some more status info? I'd like
> to add a wiki page for the board, similar to this one:
>
> http://www.coreboot.org/ASUS_P2B
>   

Just reading that page... it says level 2 cache is not enabled...
However, the cpu driver (model_6xx_init.c) says:

static void model_6xx_init(device_t dev)
{
        /* Turn on caching if we haven't already */
        x86_enable_cache();
        x86_setup_mtrrs(36);
        x86_mtrr_check();

        /* Update the microcode */
        intel_update_microcode(microcode_updates);

        /* Enable the local cpu apics */
        setup_lapic();
};


So it should be enough to add your CPU to the cpu_table in order to get
L2 cache enabled.


Stefan

Patch

Index: src/mainboard/Kconfig
===================================================================
--- src/mainboard/Kconfig	(revision 5355)
+++ src/mainboard/Kconfig	(working copy)
@@ -96,6 +96,8 @@ 
 	bool "VIA"
 config VENDOR_WINENT
 	bool "Win Enterprises"
+config VENDOR_NOKIA
+	bool "Nokia"
 
 endchoice
 
@@ -359,6 +361,11 @@ 
 	default "Win Enterprise"
 	depends on VENDOR_WINENT
 
+config MAINBOARD_VENDOR
+	string
+	default "Nokia"
+	depends on VENDOR_NOKIA
+
 source "src/mainboard/a-trend/Kconfig"
 source "src/mainboard/abit/Kconfig"
 source "src/mainboard/advantech/Kconfig"
@@ -405,6 +412,7 @@ 
 source "src/mainboard/tyan/Kconfig"
 source "src/mainboard/via/Kconfig"
 source "src/mainboard/winent/Kconfig"
+source "src/mainboard/nokia/Kconfig"
 
 config BOARD_ROMSIZE_KB_128
 	bool
Index: src/mainboard/nokia/Kconfig
===================================================================
--- src/mainboard/nokia/Kconfig	(revision 0)
+++ src/mainboard/nokia/Kconfig	(revision 0)
@@ -0,0 +1,29 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_NOKIA
+
+##source "src/mainboard/nokia/ip330/Kconfig"
+source "src/mainboard/nokia/ip530/Kconfig"
+
+endchoice
+
Index: src/mainboard/nokia/ip530/Kconfig
===================================================================
--- src/mainboard/nokia/ip530/Kconfig	(revision 0)
+++ src/mainboard/nokia/ip530/Kconfig	(revision 0)
@@ -0,0 +1,54 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_NOKIA_IP530
+	bool "IP530"
+	select ARCH_X86
+##	select CPU_INTEL_SLOT_1
+	select CPU_INTEL_SOCKET_PGA370
+	select NORTHBRIDGE_INTEL_I440BX
+	select SOUTHBRIDGE_INTEL_I82371EB
+##	select SUPERIO_WINBOND_W83977TF
+	select SUPERIO_SMSC_SMSCSUPERIO
+	select ROMCC
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+	string
+	default nokia/ip530
+	depends on BOARD_NOKIA_IP530
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "IP530"
+	depends on BOARD_NOKIA_IP530
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_NOKIA_IP530
+
+config IRQ_SLOT_COUNT
+	int
+	default 6
+	depends on BOARD_NOKIA_IP530
+
Index: src/mainboard/nokia/ip530/romstage.c
===================================================================
--- src/mainboard/nokia/ip530/romstage.c	(revision 0)
+++ src/mainboard/nokia/ip530/romstage.c	(revision 0)
@@ -0,0 +1,71 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/serial.c"
+#include "console/console.c"
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV( 0x3f0, SMSCSUPERIO_SP1 )
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i440bx/raminit.c"
+#include "northbridge/intel/i440bx/debug.c"
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	smscsuperio_enable_serial( SERIAL_DEV, CONFIG_TTYS0_BASE );
+	uart_init();
+	console_init();
+	report_bist_failure( bist );
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV( 0, 7, 0 ) ); /* ISA bridge at 00:07.0. */
+
+	enable_smbus();
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 640 * 1024); */
+}
+
Index: src/mainboard/nokia/ip530/devicetree.cb
===================================================================
--- src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
+++ src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
@@ -0,0 +1,81 @@ 
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370		# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+	chip superio/smsc/smscsuperio	# Super I/O FDC 37C878
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 3f0.4 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.7 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.9 on		# Game port
+            io 0x60 = 0x201
+          end
+          device pnp 3f0.a on		# Power-management events (PME)
+            io 0x60 = 0x600
+          end
+          device pnp 3f0.b on		# MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+    device pci 0d.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
+    end
+    device pci 0e.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
+    end
+    device pci 0f.0 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
+    end
+    device pci 0f.1 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
+    end
+  end
+  device pci_domain 1 on		# PCI domain 01
+    device pci 00.0 on 		# PCI bridge: Digital Equipment Corporation DECchip 21150 (rev 06) (prog-if 00 [Normal decode])
+    end
+  end
+  device pci_domain 2 on		# PCI domain 02
+    device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
+    end
+    device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
+    end
+  end
+end
+
Index: src/mainboard/nokia/ip530/asus_p2b_irq_tables.c
===================================================================
--- src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)
+++ src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)
@@ -0,0 +1,49 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x54,			/* Checksum */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table( unsigned long addr )
+{
+	return ( copy_pirq_routing_table( addr ) );
+}
Index: src/mainboard/nokia/ip530/irq_tables.c
===================================================================
--- src/mainboard/nokia/ip530/irq_tables.c	(revision 0)
+++ src/mainboard/nokia/ip530/irq_tables.c	(revision 0)
@@ -0,0 +1,53 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 6,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x07 << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x36,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
+		{0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
+		{0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
+		{0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
+		{0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
+
Index: src/mainboard/nokia/ip530/chip.h
===================================================================
--- src/mainboard/nokia/ip530/chip.h	(revision 0)
+++ src/mainboard/nokia/ip530/chip.h	(revision 0)
@@ -0,0 +1,22 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
Index: src/mainboard/nokia/ip530/mainboard.c
===================================================================
--- src/mainboard/nokia/ip530/mainboard.c	(revision 0)
+++ src/mainboard/nokia/ip530/mainboard.c	(revision 0)
@@ -0,0 +1,26 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME( "NOKIA IP530 Mainboard" )
+};
Index: src/northbridge/intel/i440bx/raminit.h
===================================================================
--- src/northbridge/intel/i440bx/raminit.h	(revision 5355)
+++ src/northbridge/intel/i440bx/raminit.h	(working copy)
@@ -22,9 +22,9 @@ 
 #define RAMINIT_H
 
 /* The 440BX supports up to four (single- or double-sided) DIMMs. */
-#define DIMM_SOCKETS 4
+#define DIMM_SOCKETS	4
 
 /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
-#define DIMM_SPD_BASE 0x50
+#define DIMM_SPD_BASE	0x50
 
 #endif				/* RAMINIT_H */