From patchwork Sun Apr 11 23:15:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [RFC] ACPI for ASUS P2B (Intel 440BX/82371EB) Date: Sun, 11 Apr 2010 23:15:29 -0000 From: Idwer Vollering X-Patchwork-Id: 1223 Message-Id: To: coreboot@coreboot.org This patch adds preliminary and untested ACPI support to Intel 440BX/82371EB (e.g. ASUS P2B and its variants/similar boards). It focuses on an/the ASUS P2B which comes with three ram slots, hence the change to src/northbridge/intel/i440bx/raminit.c. Some parts are based on code from other boards and need some work. It is also based on a patch [1] from Keith Hui: in the attached patch parts of src/southbridge/intel/i82371eb/i82371.h are and src/southbridge/intel/i82371eb/i82371eb_smbus.c is (C) Keith Hui. Todo: - create PRT objects - finish/fix FADT - finish all other ACPI tables (RSDT, RSDP, DSDT etcetera) - PIRQ routing - standby/suspend - ? Not Signing-off-by at this point. Idwer [1] http://www.coreboot.org/pipermail/coreboot/2010-March/056996.html Index: src/southbridge/intel/i82371eb/i82371eb_fadt.c =================================================================== --- src/southbridge/intel/i82371eb/i82371eb_fadt.c (revision 0) +++ src/southbridge/intel/i82371eb/i82371eb_fadt.c (revision 0) @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007, 2009 Rudolf Marek + * Copyright (C) 2010 Idwer Vollering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on src/southbridge/via/vt8237r/vt8237_fadt.c */ + +#include +#include +#include +#include +/* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI */ +#include +#include "i82371eb.h" /* PM_IO_BASE */ + +/** + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + device_t dev; + + /* Power management controller */ + dev = dev_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */ + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 4; + memcpy(header->oem_id, "COREBO", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 42; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = PM_IO_BASE; /* i82371eb.h */ +// fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; // 0x4 +// fadt->pm1b_cnt_blk = 0x0; +// fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; // 0x8 + fadt->gpe0_blk = PM_IO_BASE + GPSTS; // 0xc +// fadt->gpe1_blk = 0x0; +// fadt->gpe1_base = 0; +// fadt->gpe1_blk_len = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; +// fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; + fadt->p_lvl3_lat = 900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ + fadt->iapc_boot_arch = 0xb; + /* check me */ + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + +// fadt->x_pm1b_evt_blk.space_id = 1; +// fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; +// fadt->x_pm1b_evt_blk.bit_offset = 0; +// fadt->x_pm1b_evt_blk.resv = 0; +// fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; +// fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + +// fadt->x_pm1b_cnt_blk.space_id = 1; +// fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; +// fadt->x_pm1b_cnt_blk.bit_offset = 0; +// fadt->x_pm1b_cnt_blk.resv = 0; +// fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; +// fadt->x_pm1b_cnt_blk.addrh = 0x0; + +// fadt->x_pm2_cnt_blk.space_id = 1; +// fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; +// fadt->x_pm2_cnt_blk.bit_offset = 0; +// fadt->x_pm2_cnt_blk.resv = 0; +// fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; +// fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + +// fadt->x_gpe1_blk.space_id = 1; +// fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; +// fadt->x_gpe1_blk.bit_offset = 0; +// fadt->x_gpe1_blk.resv = 0; +// fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; +// fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc (revision 5408) +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2007 Uwe Hermann +## Copyright (C) 2010 Idwer Vollering ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -26,3 +27,4 @@ driver-y += i82371eb_reset.o #initobj-y += i82371eb_early_rom.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.o Index: src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- src/southbridge/intel/i82371eb/i82371eb.h (revision 5408) +++ src/southbridge/intel/i82371eb/i82371eb.h (working copy) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Uwe Hermann + * Copyright (C) 2010 Keith Hui + * Copyright (C) 2010 Idwer Vollering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -54,7 +56,26 @@ /* Power management (ACPI) */ #define PMBA 0x40 /* Power management base address */ #define PMREGMISC 0x80 /* Miscellaneous power management */ +#define PMCNTRL 0x04 /* Power Management Control */ +#define PMTMR 0x08 /* Power Management Timer */ +#define GPSTS 0x0c /* General Purpose Status */ +/* Device resources */ +#define DEVRESA 0x5c /* Device Resource A */ +#define DEVRESB 0x60 /* Device Resource B */ +#define DEVRESC 0x64 /* Device Resource C */ +#define DEVRESD 0x50 /* Device Resource D */ +#define DEVRESE 0x68 /* Device Resource E */ +#define DEVRESF 0x6c /* Device Resource F */ +#define DEVRESG 0x70 /* Device Resource G */ +#define DEVRESH 0x74 /* Device Resource H */ +#define DEVRESI 0x78 /* Device Resource I */ +#define DEVRESJ 0x7c /* Device Resource J */ + +/* Device activity */ +#define DEVACTA 0x54 /* Device Activity A */ +#define DEVACTB 0x58 /* Device Activity B */ + /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ @@ -73,4 +94,7 @@ #define ISA (1 << 0) /* Select ISA */ #define EIO (0 << 0) /* Select EIO */ +/* Power Management Base Address */ +#define PM_IO_BASE 0xe400 + #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- src/southbridge/intel/i82371eb/i82371eb_smbus.c (revision 5408) +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Uwe Hermann + * Copyright (C) 2010 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +26,57 @@ #include #include "i82371eb.h" -/* TODO: Needed later? */ +/* Table format: register, bitmask, value. */ +static const u8 register_values[] = { + /* DEVRESE - Device Resource E + * 0x68 - 0x6A + * + * [23:21] Reserved + * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12) + * 0 = Enable PCI bus decode for accesses to the I/O address + * range selected by the IBASE_DEV12 and IMASK_DEV12 fields + * 1 = Disable + * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12) + * Specifies the 4-bit I/O base address mask used to determine + * the IO address range size for device 12 accesses. + * IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a + * bit position indicates that the corresponding address bit is + * masked (i.e. ignored) when performing the decode. Note that + * programming these bits to certain patterns (such as '1001') + * results in a split address range. + * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12) + * Specifies the 16-bit I/O base address range (AD[15:0]) for the + * device 12 I/O range. When this field is combined with IMASK_DEV12 + * field, an I/O range is defined starting from the base address + * register value to the size defined by the mask register. + */ + // Set device 12 I/O range at 0xe404-0xe405 and enable. + DEVRESE + 0, 0x00, 0x04, + DEVRESE + 1, 0x00, 0xe4, + DEVRESE + 2, 0x00, 0x11, +}; + +static void pwrmgt_init(struct device *dev) +{ + int i, max; + u8 reg; + + /* Sets the base address of power management ports. */ + pci_write_config16(dev, PMBA, PM_IO_BASE | 1); + + /* Initialize other aspects of PIIX4 power management, + * using the same approach in i440bx/raminit.c. */ + max = sizeof(register_values); + + /* Set registers as specified in the register_values[] array. */ + for (i = 0; i < max; i += 3) { + reg = pci_read_config8(dev, register_values[i]); + reg &= register_values[i + 1]; + reg |= register_values[i + 2]; + pci_write_config8(dev, register_values[i], reg); + } +} + static const struct smbus_bus_operations lops_smbus_bus = { }; @@ -33,7 +84,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = pwrmgt_init, .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ Index: src/mainboard/asus/p2b/Kconfig =================================================================== --- src/mainboard/asus/p2b/Kconfig (revision 5408) +++ src/mainboard/asus/p2b/Kconfig (working copy) @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Idwer Vollering ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -27,6 +28,7 @@ select SUPERIO_WINBOND_W83977TF select ROMCC select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Index: src/mainboard/asus/p2b/devicetree.cb =================================================================== --- src/mainboard/asus/p2b/devicetree.cb (revision 5408) +++ src/mainboard/asus/p2b/devicetree.cb (working copy) @@ -50,10 +50,10 @@ register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" end end end Index: src/mainboard/asus/p2b/romstage.c =================================================================== --- src/mainboard/asus/p2b/romstage.c (revision 5408) +++ src/mainboard/asus/p2b/romstage.c (working copy) @@ -62,10 +62,12 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ + ram_check(0, 640 * 1024); + //ram_check(64 * 1024 * 1024, 640 + (64 * 1024 * 1024)); + //ram_check(256 * 1024 *1024, 640 + (256 * 1024 * 1024)); } Index: src/mainboard/asus/p2b/acpi_tables.c =================================================================== --- src/mainboard/asus/p2b/acpi_tables.c (revision 0) +++ src/mainboard/asus/p2b/acpi_tables.c (revision 0) @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Idwer Vollering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on src/mainboard/asus/a8v-e_se/acpi_tables.c */ + +#include +#include +#include +#include +#include +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ +// device_t dev; +// struct resource *res; +// +// dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); +// dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h +// if (!dev) +// return current; +// +// res = find_resource(dev, K8T890_MMCONFIG_MBAR); +// if (res) { +// current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) +// current, res->base, 0x0, 0x0, 0xff); +// } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ +// unsigned int gsi_base = 0x18; +// + /* Create all subtables for processors. */ +// current = acpi_create_madt_lapics(current); +// + /* Write SB IOAPIC. */ +// current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, +// VT8237R_APIC_ID, VT8237R_APIC_BASE, 0); +// + /* Write NB IOAPIC. */ +// current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, +// K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); +// + /* IRQ9 ACPI active low. */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); +// + /* IRQ0 -> APIC IRQ2. */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 0, 2, 0x0); +// + /* Create all subtables for processors. */ +// current = acpi_create_madt_lapic_nmis(current, +// MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); +// + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl (revision 0) +++ src/mainboard/asus/p2b/dsdt.asl (revision 0) @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Idwer Vollering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on dsdt.asl from src/mainboard/asus/a8v-e_se */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + /* Define the main processor.*/ + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + /* aaa */ + Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0, 0, 0xB }, + Package (0x04) { 0x0004FFFF, 3, 0, 0xB }, // { dev, int pin, static routing 0/1, irq } + + Package (0x04) { 0x0009FFFF, 0, 0, 0xB }, + Package (0x04) { 0x0009FFFF, 1, 0, 0xB }, + Package (0x04) { 0x0009FFFF, 2, 0, 0xB }, + Package (0x04) { 0x0009FFFF, 3, 0, 0xB }, + + Package (0x04) { 0x000AFFFF, 0, 0, 0xB }, + Package (0x04) { 0x000AFFFF, 1, 0, 0xB }, + Package (0x04) { 0x000AFFFF, 2, 0, 0xB }, + Package (0x04) { 0x000AFFFF, 3, 0, 0xB }, + + Package (0x04) { 0x000BFFFF, 0, 0, 0xB }, + Package (0x04) { 0x000BFFFF, 1, 0, 0xB }, + Package (0x04) { 0x000BFFFF, 2, 0, 0xB }, + Package (0x04) { 0x000BFFFF, 3, 0, 0xB }, + + Package (0x04) { 0x000CFFFF, 0, 0, 0xB }, + Package (0x04) { 0x000CFFFF, 1, 0, 0xB }, + Package (0x04) { 0x000CFFFF, 2, 0, 0xB }, + Package (0x04) { 0x000CFFFF, 3, 0, 0xB }, + }) + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + } +} Index: src/northbridge/intel/i440bx/raminit.c =================================================================== --- src/northbridge/intel/i440bx/raminit.c (revision 5408) +++ src/northbridge/intel/i440bx/raminit.c (working copy) @@ -925,7 +925,7 @@ set_dram_row_attributes(); /* TODO: Set SDRAMC. */ - pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */ + pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config */ /* TODO */ set_dram_buffer_strength();