Patchwork [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)

login
register
about
Submitter Idwer Vollering
Date 2010-04-15 01:20:55
Message ID <h2ufdea27e41004141820we6e0bb33wc9b8c9d1a53f954@mail.gmail.com>
Download mbox | patch
Permalink /patch/1238/
State New
Headers show

Comments

Idwer Vollering - 2010-04-15 01:20:55
2010/4/14 Keith Hui <buurin@gmail.com>

> Hi all,
>
> Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the
> rest of the PIIX4 function 3 initialization.
>
> This is a summary of what I did:
>
> * I used the DSDT table from the final vendor BIOS. Not provided here
> for obvious reasons, but I can tell you how to extract it.
> * I also replicated the content of the PIIX4 function 3 config space
> after booting with vendor BIOS, as below:
>
> 00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02)
> 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 01 e4 00 00 00 00 00 20 1e 30 00 01 00 00 00 00
> 50: 00 58 19 00 c0 c8 3b 02 37 40 40 03 00 00 00 00
> 60: 90 02 e7 00 00 00 00 10 04 e4 11 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 01 e8 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00
>
> One exception is 0x90-0x91 which has the SMBus host base address. I
> kept it as 0x0f00.
>
> * Idwer is trying to build ACPI 4.0 (!) tables. Since P2B-LS is
> shipped when ACPI was still at 1.0, that's what I did. For booting XP,
> even ACPI 2.0 compliance is sufficient.
>

Fixed the ACPI version, althought I'm not booting Windows.


> This is a summary of what happens:
>
> * I can no longer get POST codes on the PCI bus. POST codes still
> appear on the ISA bus. Glad I picked a POST card that works on both
> buses.
>

What about POST codes on the serial port ? See
http://www.coreboot.org/Coreboot_Options


> * Power off does not work. The last POST code to show before complete
> kernel shutdown and hard drive spinning down is 0xF5.
> * I don't how how to enter soft suspend in Linux (silly me -_-! ), so
> I have not tested it.
>

http://acpi.sourceforge.net/documentation/sleep.html


> * the sensor appears on ISA bus port 0x290, just like vendor BIOS.
> * My SB AWE64 ISA card still got initialized and driver loaded, but no
> sound. In fact ALSA can't even do I/O to the card. That apparently is
> because PIIX4 needs to be configured to forward certain I/O port
> ranges to ISA, and some of those port ranges can be further
> configured. This would require detecting in runtime what ISA cards are
> installed, what are they, and what I/O port ranges they would use.
> Where in the source tree should I place such code? Southbridge?
>
> The changes I made are described in two attached patches, one to
> southbridge/intel/i82371eb, one to mainboard/asus/p2bls. My coreboot
> and linux boot log is also attached.
>

Attached patch: coreboot_r5439_asus_p2b_ram+keithhui-pm+acpi-wip.patch
coreboot's serial port log + dmesg and an incomplete bootlog from linux:
http://coreboot.pastebin.com/x0QTfji7


> This is also RFC and is not signed off at this point, but comments are
> welcome.
>

When is it okay to sign off :) probably when the major functions like
standby and soft poweroff/reset work like they should and the ACPI tables
are created. Oh, and irq routing..

Self quote:

> Todo:
> - create PRT objects
> - finish/fix FADT
> - finish all other ACPI tables (RSDT, RSDP, DSDT etcetera)
>

[    0.000000] ACPI: RSDP 000f7b20 00014 (v00 CORE  )
[    0.000000] ACPI: RSDT 0fff1424 00034 (v01 CORE   COREBOOT 00000000 CORE
00000000)
[    0.000000] ACPI: FACP 0fff1aa2 000F4 (v01 COREBO COREBOOT 00000000 CORE
0000002A)
[    0.000000] ACPI: DSDT 0fff1508 0059A (v01 LXBIOS LXB-DSDT 00000001 INTL
20090521)
[    0.000000] ACPI: FACS 0fff14c8 00040
[    0.000000] ACPI: APIC 0fff1b96 0003E (v01 CORE   COREBOOT 00000000 CORE
00000000)
[    0.000000] ACPI: MCFG 0fff1bd4 0002C (v01 CORE   COREBOOT 00000000 CORE
00000000)
[    0.000000] ACPI: SRAT 0fff1c00 00030 (v01 CORE   COREBOOT 00000000 CORE
00000000)


> - PIRQ routing
>

[    1.378731] irq 9: nobody cared (try booting with the "irqpoll" option)
[    1.380003] Pid: 1, comm: swapper Not tainted 2.6.32-21-generic
#31-Ubuntu
[    1.380003] Call Trace:
<snip>
[    1.380003] Disabling IRQ #9

[    1.435077] ACPI: PCI Interrupt Link [LNKA] (IRQs) *15, disabled.
[    1.441889] ACPI: PCI Interrupt Link [LNKB] (IRQs 11) *15, disabled.
[    1.448908] ACPI: PCI Interrupt Link [LNKC] (IRQs 10) *15, disabled.
[    1.456644] ACPI: PCI Interrupt Link [LNKD] (IRQs 11) *15, disabled.
[    2.477092] ACPI: PCI Interrupt Link [LNKD] disabled and referenced, BIOS
bug

[    3.173723] irq 11: nobody cared (try booting with the "irqpoll" option)
[    3.176017] Pid: 1, comm: swapper Not tainted 2.6.32-21-generic
#31-Ubuntu
[    3.176017] Call Trace:
<snip>
[    3.176017] Disabling IRQ #11


> - standby/suspend
>

[    2.010407] input: Power Button as
/devices/LNXSYSTM:00/LNXPWRBN:00/input/input0
[    2.025108] ACPI: Power Button [PWRF]


> - ?
>



> Regards
> Keith
>

Idwer


>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
Keith Hui - 2010-04-15 16:43:33
On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering <vidwer@gmail.com> wrote:
> 2010/4/14 Keith Hui <buurin@gmail.com>
>>
>> Hi all,
>>
>> Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the
>> rest of the PIIX4 function 3 initialization.
>>
>> This is a summary of what I did:
>>
>> * I used the DSDT table from the final vendor BIOS. Not provided here
>> for obvious reasons, but I can tell you how to extract it.
>> * I also replicated the content of the PIIX4 function 3 config space
>> after booting with vendor BIOS, as below:
>>
>> 00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02)
>> 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00
>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 40: 01 e4 00 00 00 00 00 20 1e 30 00 01 00 00 00 00
>> 50: 00 58 19 00 c0 c8 3b 02 37 40 40 03 00 00 00 00
>> 60: 90 02 e7 00 00 00 00 10 04 e4 11 00 00 00 00 00
>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 90: 01 e8 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
>> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00
>>
>> One exception is 0x90-0x91 which has the SMBus host base address. I
>> kept it as 0x0f00.
>>
>> * Idwer is trying to build ACPI 4.0 (!) tables. Since P2B-LS is
>> shipped when ACPI was still at 1.0, that's what I did. For booting XP,
>> even ACPI 2.0 compliance is sufficient.
>
>
> Fixed the ACPI version, althought I'm not booting Windows.
>
Eventually we can make ACPI 2.0-compliant tables, maybe even add
support for message LED, SMI button, and even "ATK0110" support.

>>
>> This is a summary of what happens:
>>
>> * I can no longer get POST codes on the PCI bus. POST codes still
>> appear on the ISA bus. Glad I picked a POST card that works on both
>> buses.
>
> What about POST codes on the serial port ? See
> http://www.coreboot.org/Coreboot_Options
>
>>
>> * Power off does not work. The last POST code to show before complete
>> kernel shutdown and hard drive spinning down is 0xF5.
>> * I don't how how to enter soft suspend in Linux (silly me -_-! ), so
>> I have not tested it.
>
> http://acpi.sourceforge.net/documentation/sleep.html
>
Thanks. I am indeed silly. :P

>>
>> * the sensor appears on ISA bus port 0x290, just like vendor BIOS.
>> * My SB AWE64 ISA card still got initialized and driver loaded, but no
>> sound. In fact ALSA can't even do I/O to the card. That apparently is
>> because PIIX4 needs to be configured to forward certain I/O port
>> ranges to ISA, and some of those port ranges can be further
>> configured. This would require detecting in runtime what ISA cards are
>> installed, what are they, and what I/O port ranges they would use.
>> Where in the source tree should I place such code? Southbridge?
>>
>> The changes I made are described in two attached patches, one to
>> southbridge/intel/i82371eb, one to mainboard/asus/p2bls. My coreboot
>> and linux boot log is also attached.
>
> Attached patch: coreboot_r5439_asus_p2b_ram+keithhui-pm+acpi-wip.patch
> coreboot's serial port log + dmesg and an incomplete bootlog from linux:
> http://coreboot.pastebin.com/x0QTfji7
>
>>
>> This is also RFC and is not signed off at this point, but comments are
>> welcome.
>
> When is it okay to sign off :) probably when the major functions like
> standby and soft poweroff/reset work like they should and the ACPI tables
> are created. Oh, and irq routing..
>
I think when we reach a milestone eg. power off works, no ACPI
warnings from Linux, and able to boot Windows 2000 AND XP.

The last point is because I have a laptop with an ACPI implementation
that doesn't work with win2k, and I don't want that to happen.

Cheers
Keith
Carl-Daniel Hailfinger - 2010-04-15 18:19:49
On 15.04.2010 18:43, Keith Hui wrote:
> On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering <vidwer@gmail.com> wrote:
>   
>> 2010/4/14 Keith Hui <buurin@gmail.com>
>>     
>>> This is also RFC and is not signed off at this point, but comments are
>>> welcome.
>>>       
>> When is it okay to sign off :) probably when the major functions like
>> standby and soft poweroff/reset work like they should and the ACPI tables
>> are created. Oh, and irq routing..
>>
>>     
> I think when we reach a milestone eg. power off works, no ACPI
> warnings from Linux, and able to boot Windows 2000 AND XP.
>   

Please do always add your signoff. This tells us that you didn't steal
the code and that you have the right to release it.

If you think a patch is not ready, you can write that in the mail, or
add [RFC] to the subject.

Regards,
Carl-Daniel
Stefan Reinauer - 2010-04-15 21:18:32
On 4/15/10 6:43 PM, Keith Hui wrote:
> On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering <vidwer@gmail.com> wrote:

>>> This is also RFC and is not signed off at this point, but comments are
>>> welcome.
>>>       
>> When is it okay to sign off :) probably when the major functions like
>> standby and soft poweroff/reset work like they should and the ACPI tables
>> are created. Oh, and irq routing..
>>     
Signed-off does NOT mean that the code is ready, or should be included,
by any means.

Signed-off just means that the code is legally not problematic. As long
as the code is not signed off, it might cause a legal issue for anyone
working on it with you, in some weird country somewhere in the internet.

So, please, folks, if you think your code should end up on the mailing
list: Do sign if off or consider not sending it.

http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure

Thanks,
Stefan
Joseph Smith - 2010-04-15 21:51:12
On Thu, 15 Apr 2010 23:18:32 +0200, Stefan Reinauer <stepan@coresystems.de>
wrote:
> On 4/15/10 6:43 PM, Keith Hui wrote:
>> On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering <vidwer@gmail.com>
> wrote:
> 
>>>> This is also RFC and is not signed off at this point, but comments are
>>>> welcome.
>>>>       
>>> When is it okay to sign off :) probably when the major functions like
>>> standby and soft poweroff/reset work like they should and the ACPI
> tables
>>> are created. Oh, and irq routing..
>>>     
> Signed-off does NOT mean that the code is ready, or should be included,
> by any means.
> 
> Signed-off just means that the code is legally not problematic. As long
> as the code is not signed off, it might cause a legal issue for anyone
> working on it with you, in some weird country somewhere in the internet.
> 
> So, please, folks, if you think your code should end up on the mailing
> list: Do sign if off or consider not sending it.
> 
> http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
> 
Hmm, So if your code is not quite complete (or not quite ready for commit)
but you think other interested developers might be able to offer help or
suggestions or reviews what do you do then?
Stefan Reinauer - 2010-04-15 21:59:38
On 4/15/10 11:51 PM, Joseph Smith wrote:
> Hmm, So if your code is not quite complete (or not quite ready for commit)
> but you think other interested developers might be able to offer help or
> suggestions or reviews what do you do then?
>   
Sign it off
Joseph Smith - 2010-04-15 22:11:28
On Thu, 15 Apr 2010 23:59:38 +0200, Stefan Reinauer <stepan@coresystems.de>
wrote:
> On 4/15/10 11:51 PM, Joseph Smith wrote:
>> Hmm, So if your code is not quite complete (or not quite ready for
> commit)
>> but you think other interested developers might be able to offer help or
>> suggestions or reviews what do you do then?
>>   
> Sign it off
> 
Ok thanks for clarifying.
So it is ok to sign off, but just notate that it is not ready for commit
yet?
Carl-Daniel Hailfinger - 2010-04-15 23:39:52
On 16.04.2010 00:11, Joseph Smith wrote:
> On Thu, 15 Apr 2010 23:59:38 +0200, Stefan Reinauer <stepan@coresystems.de>
> wrote:
>   
>> On 4/15/10 11:51 PM, Joseph Smith wrote:
>>     
>>> Hmm, So if your code is not quite complete (or not quite ready for
>>> commit)
>>> but you think other interested developers might be able to offer help or
>>> suggestions or reviews what do you do then?
>>>   
>>>       
>> Sign it off
>>     
> Ok thanks for clarifying.
> So it is ok to sign off, but just notate that it is not ready for commit
> yet?
>   

Absolutely YES!


Regards,
Carl-Daniel
Keith Hui - 2010-04-17 03:15:58
I'll sign off on my next RFC, although as previously said, I'll say
it's ready for commit only when I made a breakthrough like when I can
power off.

At that time I'd also like to see Idwer sign off on it too. You can go
ahead and construct ACPI 2.0 compliant tables. I'm working off a DSDT
table derived from the vendor BIOS and that could be a problem, at
least legally.

Now, technical question.

Stefan gave me these inputs:

--------------
Date: Wed, 14 Apr 2010 08:31:37 +0200
From: Stefan Reinauer <stepan@coresystems.de>
To: coreboot@coreboot.org
Subject: Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel
       440BX/82371EB)
Message-ID: <4BC56149.3030707@coresystems.de>
Content-Type: text/plain; charset="iso-8859-1"

On 4/14/10 5:54 AM, Keith Hui wrote:
> irq 9: nobody cared (try booting with the "irqpoll" option)
This is caused by setting fadt->sci_int without an irqoverride source in
the MADT.

       current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
                current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL |
MP_IRQ_POLARITY_HIGH);


Generally your fadt looks a bit off, still:
+    fadt->sci_int = 9; // APM_CNT
This is not APM control but the sci interrupt
+    fadt->smi_cmd = 0;
This should be APM_CNT
+    fadt->acpi_enable = 0xa1; // ACPI_ENABLE
+    fadt->acpi_disable = 0xa0; // ACPI_DISABLE
These two should be zero unless you have an SMM handler
+    fadt->s4bios_req = 0x0;
+    fadt->pstate_cnt = 0x0;

With SMM it should look like this, assuming the APM_CNT port is 0xb2 on
the 82371 too. (It is on the ICHx chips)

#define APM_CNT         0xb2
#define   CST_CONTROL   0x85
#define   PST_CONTROL   0x80
#define   ACPI_DISABLE  0x1e
#define   ACPI_ENABLE   0xe1

       fadt->sci_int = 0x9;
       fadt->smi_cmd = APM_CNT;
       fadt->acpi_enable = ACPI_ENABLE;
       fadt->acpi_disable = ACPI_DISABLE;
       fadt->s4bios_req = 0x0;
       fadt->pstate_cnt = PST_CONTROL;
       ...
       fadt->cst_cnt = CST_CONTROL;

--------------
I checked the PIIX4 datasheet, the APM_CNT is indeed at 0xb2, with
0xb3 also available to pass data. Writes to 0xb2 triggers SMI# when
thus enabled and this ACPI enable/disable method expects writing one
byte to one port to accomplish it all.

On our boards, this is still correct:
#define   ACPI_DISABLE  0xa0
#define   ACPI_ENABLE   0xa1

I checked the OEM DSDT and found POST debug code. 0xF5 does indeed
mean some DSDT code is called when the machine is about to be put into
S5 - soft off. Of course, I was trying to power down.

It means I need to write an SMI handler. Anyone has an easily
understandable primer on it? How is the coreboot architecture for SMI
handler? I traced some files and don't see the RSM instruction
anywhere?

PIIX4 supports only one 128KB SMRAM from 0xA0000-0xBFFFF. P6 family
CPUs power up assuming this SMRAM is based at 0x30000. It can (and
will have to be) relocated, but it can only be done INSIDE SMM mode
ie. the SMI handler. I haven't dug deep enough at say the i82830 SMI
handler, but any clean idea on how to do this? OEM BIOS has three
instances of RSM instructions, implying 3 different SMI handlers for
different purposes. Analysis is still ongoing.

Now, Idwer, when I am done, I'll need you to test it as well. I
compared the ACPI tables of our boards - at least the ones I can
extract straight out of the OEM BIOS images - and they are identical
except for a longer PCI IRQ routing table for the added onboard
peripherals. So the ACPI work of either of us, should work for us
both, well me if the additional IRQ routing added back in.

Thanks
Keith

Patch

Index: src/southbridge/intel/i82371eb/i82371eb_fadt.c

===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_fadt.c	(revision 0)

+++ src/southbridge/intel/i82371eb/i82371eb_fadt.c	(revision 0)

@@ -0,0 +1,166 @@ 

+/*

+ * This file is part of the coreboot project.

+ *

+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>

+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>

+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program; if not, write to the Free Software

+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA

+ */

+

+/* Based on src/southbridge/via/vt8237r/vt8237_fadt.c */

+

+#include <string.h>

+#include <arch/acpi.h>

+#include <device/device.h>

+#include <device/pci.h>

+/* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI */

+#include <device/pci_ids.h>

+#include "i82371eb.h" /* PM_IO_BASE */

+

+/**

+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.

+ */

+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)

+{

+	acpi_header_t *header = &(fadt->header);

+	device_t dev;

+

+	/* Power management controller */

+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,

+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */

+

+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));

+	memcpy(header->signature, "FACP", 4);

+	header->length = 244;

+	header->revision = 1;

+	memcpy(header->oem_id, "COREBO", 6);

+	memcpy(header->oem_table_id, "COREBOOT", 8);

+	memcpy(header->asl_compiler_id, "CORE", 4);

+	header->asl_compiler_revision = 42;

+

+//	fadt->firmware_ctrl = (u32)facs;

+	fadt->dsdt = (u32)dsdt;

+//	fadt->preferred_pm_profile = 0;

+	fadt->sci_int = 9;

+	fadt->smi_cmd = 0;

+	fadt->acpi_enable = 0;

+	fadt->acpi_disable = 0;

+	fadt->s4bios_req = 0x0;

+	fadt->pstate_cnt = 0x0;

+

+	fadt->pm1a_evt_blk = PM_IO_BASE; /* i82371eb.h */

+//	fadt->pm1b_evt_blk = 0x0;

+	fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; // 0x4

+//	fadt->pm1b_cnt_blk = 0x0;

+//	fadt->pm2_cnt_blk = 0x0;

+	fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; // 0x8

+	fadt->gpe0_blk = PM_IO_BASE + GPSTS; // 0xc

+//	fadt->gpe1_blk = 0x0;

+//	fadt->gpe1_base = 0;

+//	fadt->gpe1_blk_len = 0;

+

+	fadt->pm1_evt_len = 4;

+	fadt->pm1_cnt_len = 2;

+//	fadt->pm2_cnt_len = 0;

+	fadt->pm_tmr_len = 4;

+	fadt->gpe0_blk_len = 4;

+

+	fadt->cst_cnt = 0;

+	fadt->p_lvl2_lat = 90;

+	fadt->p_lvl3_lat = 900;

+	fadt->flush_size = 0;

+	fadt->flush_stride = 0;

+	fadt->duty_offset = 0;

+	fadt->duty_width = 1;	//??

+	fadt->day_alrm = 0x7d;

+	fadt->mon_alrm = 0x7e;

+	fadt->century = 0x32;

+	/* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */

+	fadt->iapc_boot_arch = 0xb;

+	/* check me */

+	fadt->flags = 0xa5;

+

+	fadt->reset_reg.space_id = 0;

+	fadt->reset_reg.bit_width = 0;

+	fadt->reset_reg.bit_offset = 0;

+	fadt->reset_reg.resv = 0;

+	fadt->reset_reg.addrl = 0x0;

+	fadt->reset_reg.addrh = 0x0;

+

+	fadt->reset_value = 0;

+	fadt->x_firmware_ctl_l = (u32)facs;

+	fadt->x_firmware_ctl_h = 0;

+	fadt->x_dsdt_l = (u32)dsdt;

+	fadt->x_dsdt_h = 0;

+

+	fadt->x_pm1a_evt_blk.space_id = 1;

+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;

+	fadt->x_pm1a_evt_blk.bit_offset = 0;

+	fadt->x_pm1a_evt_blk.resv = 0;

+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;

+	fadt->x_pm1a_evt_blk.addrh = 0x0;

+

+//	fadt->x_pm1b_evt_blk.space_id = 1;

+//	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;

+//	fadt->x_pm1b_evt_blk.bit_offset = 0;

+//	fadt->x_pm1b_evt_blk.resv = 0;

+//	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;

+//	fadt->x_pm1b_evt_blk.addrh = 0x0;

+

+	fadt->x_pm1a_cnt_blk.space_id = 1;

+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;

+	fadt->x_pm1a_cnt_blk.bit_offset = 0;

+	fadt->x_pm1a_cnt_blk.resv = 0;

+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;

+	fadt->x_pm1a_cnt_blk.addrh = 0x0;

+

+//	fadt->x_pm1b_cnt_blk.space_id = 1;

+//	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;

+//	fadt->x_pm1b_cnt_blk.bit_offset = 0;

+//	fadt->x_pm1b_cnt_blk.resv = 0;

+//	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;

+//	fadt->x_pm1b_cnt_blk.addrh = 0x0;

+

+//	fadt->x_pm2_cnt_blk.space_id = 1;

+//	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;

+//	fadt->x_pm2_cnt_blk.bit_offset = 0;

+//	fadt->x_pm2_cnt_blk.resv = 0;

+//	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;

+//	fadt->x_pm2_cnt_blk.addrh = 0x0;

+

+	fadt->x_pm_tmr_blk.space_id = 1;

+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;

+	fadt->x_pm_tmr_blk.bit_offset = 0;

+	fadt->x_pm_tmr_blk.resv = 0;

+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;

+	fadt->x_pm_tmr_blk.addrh = 0x0;

+

+	fadt->x_gpe0_blk.space_id = 1;

+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;

+	fadt->x_gpe0_blk.bit_offset = 0;

+	fadt->x_gpe0_blk.resv = 0;

+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;

+	fadt->x_gpe0_blk.addrh = 0x0;

+

+//	fadt->x_gpe1_blk.space_id = 1;

+//	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;

+//	fadt->x_gpe1_blk.bit_offset = 0;

+//	fadt->x_gpe1_blk.resv = 0;

+//	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;

+//	fadt->x_gpe1_blk.addrh = 0x0;

+

+	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));

+}

Index: src/southbridge/intel/i82371eb/Makefile.inc

===================================================================
--- src/southbridge/intel/i82371eb/Makefile.inc	(revision 5439)

+++ src/southbridge/intel/i82371eb/Makefile.inc	(working copy)

@@ -2,6 +2,7 @@ 

 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -26,3 +27,4 @@ 

 driver-y +=  i82371eb_reset.o
 
 #initobj-y += i82371eb_early_rom.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.o

Index: src/southbridge/intel/i82371eb/i82371eb.h

===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.h	(revision 5439)

+++ src/southbridge/intel/i82371eb/i82371eb.h	(working copy)

@@ -2,6 +2,8 @@ 

  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>

+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -54,7 +56,26 @@ 

 /* Power management (ACPI) */
 #define PMBA		0x40	/* Power management base address */
 #define PMREGMISC	0x80	/* Miscellaneous power management */
+#define PMCNTRL		0x04	/* Power Management Control */

+#define PMTMR		0x08	/* Power Management Timer */

+#define GPSTS		0x0c	/* General Purpose Status */

 
+/* Device resources */

+#define DEVRESA		0x5c	/* Device Resource A */

+#define DEVRESB		0x60	/* Device Resource B */

+#define DEVRESC		0x64	/* Device Resource C */

+#define DEVRESD		0x50	/* Device Resource D */

+#define DEVRESE		0x68	/* Device Resource E */

+#define DEVRESF		0x6c	/* Device Resource F */

+#define DEVRESG		0x70	/* Device Resource G */

+#define DEVRESH		0x74	/* Device Resource H */

+#define DEVRESI		0x78	/* Device Resource I */

+#define DEVRESJ		0x7c	/* Device Resource J */

+

+/* Device activity */

+#define DEVACTA		0x54	/* Device Activity A */

+#define DEVACTB		0x58	/* Device Activity B */

+

 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
@@ -73,4 +94,13 @@ 

 #define ISA			(1 << 0)  /* Select ISA */
 #define EIO			(0 << 0)  /* Select EIO */
 
+/* Power Management Base Address */

+#define PM_IO_BASE 0xe400

+

+/* fix this description */

+#define PIRQA 0xB

+#define PIRQB 0xB

+#define PIRQC 0xB

+#define PIRQD 0xB

+

 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c

===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c	(revision 5439)

+++ src/southbridge/intel/i82371eb/i82371eb_smbus.c	(working copy)

@@ -2,6 +2,7 @@ 

  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>

  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,7 +26,45 @@ 

 #include <device/smbus.h>
 #include "i82371eb.h"
 
-/* TODO: Needed later? */

+/* Table format: register, bitmask, value. */

+static const u8 register_values[] = {

+	/* DEVRESE - Device Resource E

+	 * 0x68 - 0x6A

+	 *

+	 * [23:21] Reserved

+	 * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12)

+	 *         0 = Enable PCI bus decode for accesses to the I/O address 

+	 *             range selected by the IBASE_DEV12 and IMASK_DEV12 fields

+	 *         1 = Disable

+	 * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12)

+	 *         Specifies the 4-bit I/O base address mask used to determine 

+	 *         the IO address range size for device 12 accesses. 

+	 *         IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a 

+	 *         bit position indicates that the corresponding address bit is 

+	 *         masked (i.e. ignored) when performing the decode. Note that 

+	 *         programming these bits to certain patterns (such as '1001') 

+	 *         results in a split address range.

+	 * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12)

+	 *         Specifies the 16-bit I/O base address range (AD[15:0]) for the 

+	 *         device 12 I/O range. When this field is combined with IMASK_DEV12 

+	 *         field, an I/O range is defined starting from the base address 

+	 *         register value to the size defined by the mask register.

+	 */

+	// Set device 12 I/O range at 0xe404-0xe405 and enable.

+	DEVRESE + 0, 0x00, 0x04,

+	DEVRESE + 1, 0x00, 0xe4,

+	DEVRESE + 2, 0x00, 0x11,

+};

+

+static void pwrmgt_init(struct device *dev)

+{

+	/* Sets the base address of power management ports. */

+	pci_write_config16(dev, PMBA, PM_IO_BASE | 1);

+

+	u8 val = pci_read_config8(dev, PMREGMISC);

+	pci_write_config8(dev, PMREGMISC, val | 1);

+}

+

 static const struct smbus_bus_operations lops_smbus_bus = {
 };
 
@@ -33,7 +72,7 @@ 

 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,

+	.init			= pwrmgt_init,

 	.scan_bus		= scan_static_bus,
 	.enable			= 0,
 	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
Index: src/mainboard/asus/p2b/Kconfig

===================================================================
--- src/mainboard/asus/p2b/Kconfig	(revision 5439)

+++ src/mainboard/asus/p2b/Kconfig	(working copy)

@@ -2,6 +2,7 @@ 

 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -27,6 +28,7 @@ 

 	select SUPERIO_WINBOND_W83977TF
 	select ROMCC
 	select HAVE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES

 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
 
Index: src/mainboard/asus/p2b/devicetree.cb

===================================================================
--- src/mainboard/asus/p2b/devicetree.cb	(revision 5439)

+++ src/mainboard/asus/p2b/devicetree.cb	(working copy)

@@ -50,10 +50,10 @@ 

       register "ide1_enable" = "1"
       register "ide_legacy_enable" = "1"
       # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"

-      register "ide0_drive1_udma33_enable" = "0"

-      register "ide1_drive0_udma33_enable" = "0"

-      register "ide1_drive1_udma33_enable" = "0"

+      register "ide0_drive0_udma33_enable" = "1"

+      register "ide0_drive1_udma33_enable" = "1"

+      register "ide1_drive0_udma33_enable" = "1"

+      register "ide1_drive1_udma33_enable" = "1"

     end
   end
 end
Index: src/mainboard/asus/p2b/romstage.c

===================================================================
--- src/mainboard/asus/p2b/romstage.c	(revision 5439)

+++ src/mainboard/asus/p2b/romstage.c	(working copy)

@@ -62,10 +62,12 @@ 

 	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */

+	dump_spd_registers();

 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */

+	ram_check(0, 640 * 1024);

+	//ram_check(64 * 1024 * 1024, 640 + (64 * 1024 * 1024));

+	//ram_check(256 * 1024 *1024, 640 + (256 * 1024 * 1024));

 }
 
Index: src/mainboard/asus/p2b/acpi_tables.c

===================================================================
--- src/mainboard/asus/p2b/acpi_tables.c	(revision 0)

+++ src/mainboard/asus/p2b/acpi_tables.c	(revision 0)

@@ -0,0 +1,145 @@ 

+/*

+ * This file is part of the coreboot project.

+ *

+ * Written by Stefan Reinauer <stepan@openbios.org>.

+ * ACPI FADT, FACS, and DSDT table support added by 

+ *

+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>

+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>

+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>

+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; version 2 of the License.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program; if not, write to the Free Software

+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA

+ */

+

+/* Based on src/mainboard/asus/a8v-e_se/acpi_tables.c */

+

+#include <console/console.h>

+#include <string.h>

+#include <arch/acpi.h>

+#include <arch/smp/mpspec.h>

+#include <device/device.h>

+#include <device/pci_ids.h>

+

+extern const unsigned char AmlCode[];

+

+unsigned long acpi_fill_slit(unsigned long current)

+{

+	// Not implemented

+	return current;

+}

+

+unsigned long acpi_fill_srat(unsigned long current)

+{

+	// Not implemented

+	return current;

+}

+

+unsigned long acpi_fill_mcfg(unsigned long current)

+{

+/*

+	device_t dev;

+

+	dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h

+	if (!dev)

+		return current;

+*/

+	return current;

+}

+

+unsigned long acpi_fill_madt(unsigned long current)

+{

+	/* Create all subtables for processors. */

+	current = acpi_create_madt_lapics(current);

+

+	/* IRQ9 ACPI active low. */

+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);

+

+	return current;

+}

+

+unsigned long write_acpi_tables(unsigned long start)

+{

+	unsigned long current;

+	acpi_rsdp_t *rsdp;

+	acpi_srat_t *srat;

+	acpi_rsdt_t *rsdt;

+	acpi_madt_t *madt;

+	acpi_mcfg_t *mcfg;

+	acpi_fadt_t *fadt;

+	acpi_facs_t *facs;

+	acpi_header_t *dsdt;

+

+	/* Align ACPI tables to 16 byte. */

+	start = (start + 0x0f) & -0x10;

+	current = start;

+

+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);

+

+	/* We need at least an RSDP and an RSDT table. */

+	rsdp = (acpi_rsdp_t *) current;

+	current += sizeof(acpi_rsdp_t);

+	rsdt = (acpi_rsdt_t *) current;

+	current += sizeof(acpi_rsdt_t);

+

+	/* Clear all table memory. */

+	memset((void *) start, 0, current - start);

+

+	acpi_write_rsdp(rsdp, rsdt, NULL);

+	acpi_write_rsdt(rsdt);

+

+	/* We explicitly add these tables later on: */

+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");

+	facs = (acpi_facs_t *) current;

+	current += sizeof(acpi_facs_t);

+	acpi_create_facs(facs);

+

+	dsdt = (acpi_header_t *)current;

+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));

+	current += dsdt->length;

+	memcpy(dsdt, &AmlCode, dsdt->length);

+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */

+	dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);

+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,

+		     dsdt->length);

+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");

+

+	fadt = (acpi_fadt_t *) current;

+	current += sizeof(acpi_fadt_t);

+

+	acpi_create_fadt(fadt, facs, dsdt);

+	acpi_add_table(rsdp, fadt);

+

+	/* If we want to use HPET timers Linux wants it in MADT. */

+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");

+	madt = (acpi_madt_t *) current;

+	acpi_create_madt(madt);

+	current += madt->header.length;

+	acpi_add_table(rsdp, madt);

+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");

+	mcfg = (acpi_mcfg_t *) current;

+	acpi_create_mcfg(mcfg);

+	current += mcfg->header.length;

+	acpi_add_table(rsdp, mcfg);

+

+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");

+	srat = (acpi_srat_t *) current;

+	acpi_create_srat(srat);

+	current += srat->header.length;

+	acpi_add_table(rsdp, srat);

+

+	printk(BIOS_INFO, "ACPI: done.\n");

+	return current;

+}

Index: src/mainboard/asus/p2b/dsdt.asl

===================================================================
--- src/mainboard/asus/p2b/dsdt.asl	(revision 0)

+++ src/mainboard/asus/p2b/dsdt.asl	(revision 0)

@@ -0,0 +1,417 @@ 

+/*

+ * This file is part of the coreboot project.

+ *

+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>

+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>

+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; version 2 of the License.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program; if not, write to the Free Software

+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA

+ */

+

+/* Based on dsdt.asl from src/mainboard/asus/a8v-e_se */

+

+/*

+ * ISA portions taken from QEMU acpi-dsdt.dsl.

+ */

+

+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)

+{

+	/* Define the main processor.*/

+	Scope (\_PR)

+	{

+		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}

+		Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}

+	}

+

+	/* For now only define 2 power states:

+	 *  - S0 which is fully on

+	 *  - S5 which is soft off

+	 * Any others would involve declaring the wake up methods.

+	 */

+	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })

+	Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })

+

+	/* Root of the bus hierarchy */

+	Scope (\_SB)

+	{

+		/* Top PCI device */

+		Device (PCI0)

+		{

+			Name (_HID, EisaId ("PNP0A03"))

+			Name (_ADR, 0x00)

+			Name (_UID, 0x00)

+			Name (_BBN, 0x00)

+

+			/* PCI Routing Table */

+			/* aaa */

+			Name (_PRT, Package () {

+				Package (0x04) { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },

+				Package (0x04) { 0x0004FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },

+

+				Package (0x04) { 0x0009FFFF, 0, \_SB.PCI0.LPCB.LNKD, 0 },

+				Package (0x04) { 0x0009FFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },

+				Package (0x04) { 0x0009FFFF, 2, \_SB.PCI0.LPCB.LNKB, 0 },

+				Package (0x04) { 0x0009FFFF, 3, \_SB.PCI0.LPCB.LNKC, 0 },

+

+				Package (0x04) { 0x000AFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },

+				Package (0x04) { 0x000AFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },

+				Package (0x04) { 0x000AFFFF, 2, \_SB.PCI0.LPCB.LNKA, 0 },

+				Package (0x04) { 0x000AFFFF, 3, \_SB.PCI0.LPCB.LNKB, 0 },

+

+				Package (0x04) { 0x000BFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },

+				Package (0x04) { 0x000BFFFF, 1, \_SB.PCI0.LPCB.LNKC, 0 },

+				Package (0x04) { 0x000BFFFF, 2, \_SB.PCI0.LPCB.LNKD, 0 },

+				Package (0x04) { 0x000BFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },

+

+				Package (0x04) { 0x000CFFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },

+				Package (0x04) { 0x000CFFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },

+				Package (0x04) { 0x000CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },

+				Package (0x04) { 0x000CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },

+

+			})

+

+				// Intel LPC Bus Device  - 0:7.0

+

+				Device (LPCB)

+					{

+						Name(_ADR, 0x0070000)

+

+						OperationRegion(LPC0, PCI_Config, 0x00, 0x100)

+						Field (LPC0, AnyAcc, NoLock, Preserve)

+						{

+							Offset (0x40),

+							PMBS,	16,	// PMBASE

+							Offset (0x60),	// Interrupt Routing Registers

+							PRTA,	8,

+							PRTB,	8,

+							PRTC,	8,

+							PRTD,	8,

+						}

+

+					// this should go to some other file maybe 

+

+					Device (LNKA)

+					{

+						Name (_HID, EISAID("PNP0C0F"))

+						Name (_UID, 1)

+

+						// Disable method

+						Method (_DIS, 0, Serialized)

+						{

+							Store (0x80, PRTA)

+						}

+

+						// Possible Resource Settings for this Link

+						Name (_PRS, ResourceTemplate()

+						{

+							IRQ(Level, ActiveLow, Shared)

+								//{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }

+								{ }

+						})

+

+						// Current Resource Settings for this link

+						Method (_CRS, 0, Serialized)

+						{

+							Name (RTLA, ResourceTemplate()

+							{

+								IRQ(Level, ActiveLow, Shared) {}

+							})

+							CreateWordField(RTLA, 1, IRQ0)

+

+							// Clear the WordField

+							Store (Zero, IRQ0)

+

+							// Set the bit from PRTA

+							ShiftLeft(1, And(PRTA, 0x0f), IRQ0)

+

+							Return (RTLA)

+						}

+

+						// Set Resource Setting for this IRQ link

+						Method (_SRS, 1, Serialized)

+						{

+							CreateWordField(Arg0, 1, IRQ0)

+

+							// Which bit is set?

+							FindSetRightBit(IRQ0, Local0)

+

+							Decrement(Local0)

+							Store(Local0, PRTA)

+						}

+

+						// Status

+						Method (_STA, 0, Serialized)

+						{

+							If(And(PRTA, 0x80)) {

+								Return (0x9)

+							} Else {

+								Return (0xb)

+							}

+						}

+					} // LNKA

+

+					Device (LNKB)

+					{

+						Name (_HID, EISAID("PNP0C0F"))

+						Name (_UID, 2)

+

+						// Disable method

+						Method (_DIS, 0, Serialized)

+						{

+							Store (0x80, PRTB)

+						}

+

+						// Possible Resource Settings for this Link

+						Name (_PRS, ResourceTemplate()

+						{

+							IRQ(Level, ActiveLow, Shared)

+								{ 11 }

+								//{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }

+						})

+

+						// Current Resource Settings for this link

+						Method (_CRS, 0, Serialized)

+						{

+							Name (RTLB, ResourceTemplate()

+							{

+								IRQ(Level, ActiveLow, Shared) {}

+							})

+							CreateWordField(RTLB, 1, IRQ0)

+

+							// Clear the WordField

+							Store (Zero, IRQ0)

+

+							// Set the bit from PRTB

+							ShiftLeft(1, And(PRTB, 0x0f), IRQ0)

+

+							Return (RTLB)

+						}

+

+						// Set Resource Setting for this IRQ link

+						Method (_SRS, 1, Serialized)

+						{

+							CreateWordField(Arg0, 1, IRQ0)

+

+							// Which bit is set?

+							FindSetRightBit(IRQ0, Local0)

+

+							Decrement(Local0)

+							Store(Local0, PRTB)

+						}

+

+						// Status

+						Method (_STA, 0, Serialized)

+						{

+							If(And(PRTB, 0x80)) {

+								Return (0x9)

+							} Else {

+								Return (0xb)

+							}

+						}

+					} // LNKB

+

+					Device (LNKC)

+					{

+						Name (_HID, EISAID("PNP0C0F"))

+						Name (_UID, 3)

+

+						// Disable method

+						Method (_DIS, 0, Serialized)

+						{

+							Store (0x80, PRTC)

+						}

+

+						// Possible Resource Settings for this Link

+						Name (_PRS, ResourceTemplate()

+						{

+							IRQ(Level, ActiveLow, Shared)

+								//{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }

+								{ 10 }

+						})

+

+						// Current Resource Settings for this link

+						Method (_CRS, 0, Serialized)

+						{

+							Name (RTLC, ResourceTemplate()

+							{

+								IRQ(Level, ActiveLow, Shared) {}

+							})

+							CreateWordField(RTLC, 1, IRQ0)

+

+							// Clear the WordField

+							Store (Zero, IRQ0)

+

+							// Set the bit from PRTC

+							ShiftLeft(1, And(PRTC, 0x0f), IRQ0)

+

+							Return (RTLC)

+						}

+

+						// Set Resource Setting for this IRQ link

+						Method (_SRS, 1, Serialized)

+						{

+							CreateWordField(Arg0, 1, IRQ0)

+

+							// Which bit is set?

+							FindSetRightBit(IRQ0, Local0)

+

+							Decrement(Local0)

+							Store(Local0, PRTC)

+						}

+

+						// Status

+						Method (_STA, 0, Serialized)

+						{

+							If(And(PRTC, 0x80)) {

+								Return (0x9)

+							} Else {

+								Return (0xb)

+							}

+						}

+					} // LNKC

+

+					Device (LNKD)

+					{

+						Name (_HID, EISAID("PNP0C0F"))

+						Name (_UID, 4)

+

+						// Disable method

+						Method (_DIS, 0, Serialized)

+						{

+							Store (0x80, PRTD)

+						}

+

+						// Possible Resource Settings for this Link

+						Name (_PRS, ResourceTemplate()

+						{

+							IRQ(Level, ActiveLow, Shared)

+								{ 11 }

+								//{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }

+						})

+

+						// Current Resource Settings for this link

+						Method (_CRS, 0, Serialized)

+						{

+							Name (RTLD, ResourceTemplate()

+							{

+								IRQ(Level, ActiveLow, Shared) {}

+							})

+							CreateWordField(RTLD, 1, IRQ0)

+

+							// Clear the WordField

+							Store (Zero, IRQ0)

+

+							// Set the bit from PRTD

+							ShiftLeft(1, And(PRTD, 0x0f), IRQ0)

+

+							Return (RTLD)

+						}

+

+						// Set Resource Setting for this IRQ link

+						Method (_SRS, 1, Serialized)

+						{

+							CreateWordField(Arg0, 1, IRQ0)

+

+							// Which bit is set?

+							FindSetRightBit(IRQ0, Local0)

+

+							Decrement(Local0)

+							Store(Local0, PRTD)

+						}

+

+						// Status

+						Method (_STA, 0, Serialized)

+						{

+							If(And(PRTD, 0x80)) {

+								Return (0x9)

+							} Else {

+								Return (0xb)

+							}

+						}

+					} // LNKD

+

+					// end

+

+					// now modify the PRT method to use:

+

+					//		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},

+					//		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},

+					//		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},

+					//		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},

+

+				} // LPCB

+

+			Device (ISA) {

+				Name (_ADR, 0x00110000)

+

+				/* PS/2 keyboard (seems to be important for WinXP install) */

+				Device (KBD)

+				{

+					Name (_HID, EisaId ("PNP0303"))

+					Method (_STA, 0, NotSerialized)

+					{

+						Return (0x0f)

+					}

+					Method (_CRS, 0, NotSerialized)

+					{

+						Name (TMP, ResourceTemplate () {

+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)

+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)

+							IRQNoFlags () {1}

+						})

+						Return (TMP)

+					}

+				}

+

+				/* PS/2 mouse */

+				Device (MOU)

+				{

+					Name (_HID, EisaId ("PNP0F13"))

+					Method (_STA, 0, NotSerialized)

+					{

+						Return (0x0f)

+					}

+					Method (_CRS, 0, NotSerialized)

+					{

+						Name (TMP, ResourceTemplate () {

+						     IRQNoFlags () {12}

+						})

+						Return (TMP)

+					}

+				}

+

+				/* PS/2 floppy controller */

+				Device (FDC0)

+				{

+					Name (_HID, EisaId ("PNP0700"))

+					Method (_STA, 0, NotSerialized)

+					{

+						Return (0x0f)

+					}

+					Method (_CRS, 0, NotSerialized)

+					{

+						Name (BUF0, ResourceTemplate () {

+							IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)

+							IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)

+							IRQNoFlags () {6}

+							DMA (Compatibility, NotBusMaster, Transfer8) {2}

+						})

+						Return (BUF0)

+					}

+				}

+			}

+		}

+

+	}

+}

Index: src/northbridge/intel/i440bx/raminit.c

===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(revision 5439)

+++ src/northbridge/intel/i440bx/raminit.c	(working copy)

@@ -925,7 +925,7 @@ 

 	set_dram_row_attributes();
 
 	/* TODO: Set SDRAMC. */
-	pci_write_config16(NB, SDRAMC, 0x0010);	/* SDRAMPWR=1: 4 DIMM config */

+	pci_write_config16(NB, SDRAMC, 0x0000);	/* SDRAMPWR=0: 3 DIMM config */

 
 	/* TODO */
 	set_dram_buffer_strength();