Patchwork [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)

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Submitter Idwer Vollering
Date 2010-04-26 01:55:57
Message ID <g2qfdea27e41004251855u4345e403t9eec3299d4d110b4@mail.gmail.com>
Download mbox | patch
Permalink /patch/1267/
State New
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Comments

Idwer Vollering - 2010-04-26 01:55:57
2010/4/17 Keith Hui <buurin@gmail.com>

> I'll sign off on my next RFC, although as previously said, I'll say
> it's ready for commit only when I made a breakthrough like when I can
> power off.
>
> At that time I'd also like to see Idwer sign off on it too. You can go
> ahead and construct ACPI 2.0 compliant tables. I'm working off a DSDT
> table derived from the vendor BIOS and that could be a problem, at
> least legally.
>
> Now, technical question.
>
> Stefan gave me these inputs:
>
> --------------
> Date: Wed, 14 Apr 2010 08:31:37 +0200
> From: Stefan Reinauer <stepan@coresystems.de>
> To: coreboot@coreboot.org
> Subject: Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel
>       440BX/82371EB)
> Message-ID: <4BC56149.3030707@coresystems.de>
> Content-Type: text/plain; charset="iso-8859-1"
>
> On 4/14/10 5:54 AM, Keith Hui wrote:
> > irq 9: nobody cared (try booting with the "irqpoll" option)
> This is caused by setting fadt->sci_int without an irqoverride source in
> the MADT.
>
>       current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
>                current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL |
> MP_IRQ_POLARITY_HIGH);
>
>
> Generally your fadt looks a bit off, still:
> +    fadt->sci_int = 9; // APM_CNT
> This is not APM control but the sci interrupt
> +    fadt->smi_cmd = 0;
>

smi_cmd means smi command port ?

This should be APM_CNT
> +    fadt->acpi_enable = 0xa1; // ACPI_ENABLE
> +    fadt->acpi_disable = 0xa0; // ACPI_DISABLE
> These two should be zero unless you have an SMM handler
> +    fadt->s4bios_req = 0x0;
> +    fadt->pstate_cnt = 0x0;
>
> With SMM it should look like this, assuming the APM_CNT port is 0xb2 on
> the 82371 too. (It is on the ICHx chips)
>
> #define APM_CNT         0xb2
> #define   CST_CONTROL   0x85
> #define   PST_CONTROL   0x80
> #define   ACPI_DISABLE  0x1e
> #define   ACPI_ENABLE   0xe1
>

 This should be/go in i82371eb.h


>       fadt->sci_int = 0x9;
>       fadt->smi_cmd = APM_CNT;
>       fadt->acpi_enable = ACPI_ENABLE;
>       fadt->acpi_disable = ACPI_DISABLE;
>       fadt->s4bios_req = 0x0;
>       fadt->pstate_cnt = PST_CONTROL;
>       ...
>       fadt->cst_cnt = CST_CONTROL;
>
> --------------
> I checked the PIIX4 datasheet, the APM_CNT is indeed at 0xb2, with
> 0xb3 also available to pass data. Writes to 0xb2 triggers SMI# when
> thus enabled and this ACPI enable/disable method expects writing one
> byte to one port to accomplish it all.
>

APMC at 0xb2 and APMS at 0xb3


> On our boards, this is still correct:
> #define   ACPI_DISABLE  0xa0
> #define   ACPI_ENABLE   0xa1
>
> I checked the OEM DSDT and found POST debug code. 0xF5 does indeed
> mean some DSDT code is called when the machine is about to be put into
> S5 - soft off. Of course, I was trying to power down.
>

/* For now only define 2 power states:
 *  - S0 which is fully on
 *  - S5 which is soft off
 * Any others would involve declaring the wake up methods.
 */

/* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
/*
000b / 0x0: soft off/suspend to disk (soff/std)            s5
001b / 0x1: suspend to ram (str)                s3
010b / 0x2: powered on suspend, context lost (poscl)        s1
011b / 0x3: powered on suspend, cpu context lost (posccl)    s2
100b / 0x4: powered on suspend, context maintained (pos)    s4
101b / 0x5: working (clock control)                s0
110b / 0x6: reserved
111b / 0x7: reserved
*/
Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })


S0 and S5 should be correct but since there's no SMI *yet* poweroff doesn't
work.


> It means I need to write an SMI handler. Anyone has an easily
> understandable primer on it? How is the coreboot architecture for SMI
> handler? I traced some files and don't see the RSM instruction
> anywhere?
>

Sorry, I don't know anything about SMI and a little about ACPI.
Have a look at SMI from, I believe, ICH7:
http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.cand
http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c


> PIIX4 supports only one 128KB SMRAM from 0xA0000-0xBFFFF. P6 family
> CPUs power up assuming this SMRAM is based at 0x30000. It can (and
> will have to be) relocated, but it can only be done INSIDE SMM mode
> ie. the SMI handler. I haven't dug deep enough at say the i82830 SMI
> handler, but any clean idea on how to do this? OEM BIOS has three
> instances of RSM instructions, implying 3 different SMI handlers for
> different purposes. Analysis is still ongoing.
>
> Now, Idwer, when I am done, I'll need you to test it as well. I
> compared the ACPI tables of our boards - at least the ones I can
> extract straight out of the OEM BIOS images - and they are identical
> except for a longer PCI IRQ routing table for the added onboard
> peripherals. So the ACPI work of either of us, should work for us
> both, well me if the additional IRQ routing added back in.
>
> Thanks
> Keith
>
 Still unfinished/WIP and unpolished; attaching my patch and signing off:

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Stefan Reinauer - 2010-04-26 12:16:37
On 4/26/10 3:55 AM, Idwer Vollering wrote:
>
>
>
>     Generally your fadt looks a bit off, still:
>     +    fadt->sci_int = 9; // APM_CNT
>     This is not APM control but the sci interrupt
>     +    fadt->smi_cmd = 0;
>
>
> smi_cmd means smi command port ?
yes

Patch

Index: src/southbridge/intel/i82371eb/i82371eb_fadt.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_fadt.c	(revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_fadt.c	(revision 0)
@@ -0,0 +1,164 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Based on src/southbridge/via/vt8237r/vt8237_fadt.c */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+/* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI */
+#include <device/pci_ids.h>
+#include "i82371eb.h" /* PM_IO_BASE, PMCNTRL */
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	device_t dev;
+
+	/* Power management controller */
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "COREBO", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 42;
+
+//	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = 0;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0xb2; // smi command port ?
+	fadt->acpi_enable = 0xa1;
+	fadt->acpi_disable = 0xa0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = PM_IO_BASE; /* PM_IO_BASE = 0xe400 */
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; /* PMCNTRL = 0x4 */
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; /* PMTMR = 0x8 */
+	fadt->gpe0_blk = PM_IO_BASE + GPSTS; /* GPSTS = 0xc */
+	fadt->gpe1_blk = 0x0;
+	fadt->gpe1_base = 0;
+	fadt->gpe1_blk_len = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 4;
+
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 0x5a;
+	fadt->p_lvl3_lat = 0x0384;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x0;
+	fadt->century = 0x0;
+	fadt->iapc_boot_arch = 0x0;
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
Index: src/southbridge/intel/i82371eb/Makefile.inc
===================================================================
--- src/southbridge/intel/i82371eb/Makefile.inc	(revision 5500)
+++ src/southbridge/intel/i82371eb/Makefile.inc	(working copy)
@@ -2,6 +2,7 @@ 
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -26,3 +27,6 @@ 
 driver-y +=  i82371eb_reset.o
 
 #initobj-y += i82371eb_early_rom.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.o
+obj-$(CONFIG_HAVE_SMI_HANDLER) += i82371eb_smi.o
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82371eb_smihandler.o
Index: src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.h	(revision 5500)
+++ src/southbridge/intel/i82371eb/i82371eb.h	(working copy)
@@ -2,6 +2,8 @@ 
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -40,6 +42,7 @@ 
 #define XBCS		0x4e	/* X-Bus chip select register */
 #define GENCFG		0xb0	/* General configuration register */
 #define RC		0xcf9	/* Reset control register */
+#define GLBCTL		0x28	/* Global control register */
 
 /* IDE */
 #define IDETIM_PRI	0x40	/* IDE timing register, primary channel */
@@ -54,7 +57,26 @@ 
 /* Power management (ACPI) */
 #define PMBA		0x40	/* Power management base address */
 #define PMREGMISC	0x80	/* Miscellaneous power management */
+#define PMCNTRL		0x04	/* Power Management Control */
+#define PMTMR		0x08	/* Power Management Timer */
+#define GPSTS		0x0c	/* General Purpose Status */
 
+/* Device resources */
+#define DEVRESA		0x5c	/* Device Resource A */
+#define DEVRESB		0x60	/* Device Resource B */
+#define DEVRESC		0x64	/* Device Resource C */
+#define DEVRESD		0x50	/* Device Resource D */
+#define DEVRESE		0x68	/* Device Resource E */
+#define DEVRESF		0x6c	/* Device Resource F */
+#define DEVRESG		0x70	/* Device Resource G */
+#define DEVRESH		0x74	/* Device Resource H */
+#define DEVRESI		0x78	/* Device Resource I */
+#define DEVRESJ		0x7c	/* Device Resource J */
+
+/* Device activity */
+#define DEVACTA		0x54	/* Device Activity A */
+#define DEVACTB		0x58	/* Device Activity B */
+
 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
@@ -72,5 +94,17 @@ 
 #define SSDE1			(1 << 3)  /* Secondary Drive 1 UDMA/33 */
 #define ISA			(1 << 0)  /* Select ISA */
 #define EIO			(0 << 0)  /* Select EIO */
+#define SMI_EN			(1 << 0)  /* Enable SMI# generation */
+#define EXTSMI_STS		(1 << 10) /* This is for i82371eb_smi.c:reset_smi_status() */
+#define EOS			(1 << 16) /* Enable End of SMI */
 
+/* Power Management Base Address */
+#define PM_IO_BASE 0xe400
+
+/* FIXME: description */
+#define PIRQA 0xB
+#define PIRQB 0xB
+#define PIRQC 0xB
+#define PIRQD 0xB
+
 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
Index: src/southbridge/intel/i82371eb/i82371eb_smihandler.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smihandler.c	(revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_smihandler.c	(revision 0)
@@ -0,0 +1,43 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#include <types.h>
+//#include <arch/io.h>
+//#include <arch/romcc_io.h>
+//#include <console/console.h>
+//#include <cpu/x86/cache.h>
+//#include <cpu/x86/smm.h>
+//#include <device/pci_def.h>
+//#include "i82371eb.h"
+
+void southbridge_smi_set_eos(void)
+{
+	// Not implemented
+}
+
+void southbridge_io_trap_handler(void)
+{
+	// Not implemented
+}
+
+void mainboard_io_trap_handler(void)
+{
+	// Not implemented
+}
Index: src/southbridge/intel/i82371eb/i82371eb_smi.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smi.c	(revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_smi.c	(revision 0)
@@ -0,0 +1,45 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#include <device/device.h>
+//#include <device/pci.h>
+//#include <console/console.h>
+//#include <arch/io.h>
+//#include <cpu/cpu.h>
+//#include <cpu/x86/cache.h>
+//#include <cpu/x86/smm.h>
+//#include <string.h>
+
+#include "i82371eb.h"
+
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(PMBA + EXTSMI_STS);
+	outl(reg32, PMBA + EXTSMI_STS);
+
+	return reg32;
+}
+
+void smm_init(void)
+{
+	// Not implemented
+}
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c	(revision 5500)
+++ src/southbridge/intel/i82371eb/i82371eb_smbus.c	(working copy)
@@ -2,6 +2,7 @@ 
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,6 +19,8 @@ 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h> // include fix for inb() / outw()
+#include <console/console.h> // include fix for printk()
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -25,7 +28,65 @@ 
 #include <device/smbus.h>
 #include "i82371eb.h"
 
-/* TODO: Needed later? */
+/* Table format: register, bitmask, value. */
+static const u8 register_values[] = {
+	/* DEVRESE - Device Resource E
+	 * 0x68 - 0x6A
+	 *
+	 * [23:21] Reserved
+	 * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12)
+	 *         0 = Enable PCI bus decode for accesses to the I/O address 
+	 *             range selected by the IBASE_DEV12 and IMASK_DEV12 fields
+	 *         1 = Disable
+	 * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12)
+	 *         Specifies the 4-bit I/O base address mask used to determine 
+	 *         the IO address range size for device 12 accesses. 
+	 *         IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a 
+	 *         bit position indicates that the corresponding address bit is 
+	 *         masked (i.e. ignored) when performing the decode. Note that 
+	 *         programming these bits to certain patterns (such as '1001') 
+	 *         results in a split address range.
+	 * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12)
+	 *         Specifies the 16-bit I/O base address range (AD[15:0]) for the 
+	 *         device 12 I/O range. When this field is combined with IMASK_DEV12 
+	 *         field, an I/O range is defined starting from the base address 
+	 *         register value to the size defined by the mask register.
+	 */
+	// Set device 12 I/O range at 0xe404-0xe405 and enable.
+	DEVRESE + 0, 0x00, 0x04,
+	DEVRESE + 1, 0x00, 0xe4,
+	DEVRESE + 2, 0x00, 0x11,
+};
+
+static void pwrmgt_init(struct device *dev)
+{
+	/* Sets the base address of power management ports. */
+	pci_write_config16(dev, PMBA, PM_IO_BASE | 1);
+
+	u8 val = pci_read_config8(dev, PMREGMISC);
+	pci_write_config8(dev, PMREGMISC, val | 1);
+
+	int i;
+	for (i = 0; i < 64; i++) {
+		if ((i != 14) || (i != 15))
+//			printk("REG %02x is %02x\n", inb(PM_IO_BASE + i));
+			printk(BIOS_INFO, "REG %02x is %02x\n", i, inb(PM_IO_BASE + i));
+	}
+
+	outl(0x00200004, PM_IO_BASE + 0x28);
+
+	/* Clear status events. */
+	outw(0xffff, PM_IO_BASE + 0x00);
+	outw(0xffff, PM_IO_BASE + 0xC);
+	outw(0xffff, PM_IO_BASE + 0x18);
+
+	for (i = 0; i < 64; i++) {
+		if ((i != 14) || (i != 15))
+//			printk("REG %02x is %02x\n", inb(PM_IO_BASE + i));
+			printk(BIOS_INFO, "REG %02x is %02x\n", i, inb(PM_IO_BASE + i));
+	}
+}
+
 static const struct smbus_bus_operations lops_smbus_bus = {
 };
 
@@ -33,7 +94,7 @@ 
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,
+	.init			= pwrmgt_init,
 	.scan_bus		= scan_static_bus,
 	.enable			= 0,
 	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
Index: src/mainboard/asus/p2b/Kconfig
===================================================================
--- src/mainboard/asus/p2b/Kconfig	(revision 5500)
+++ src/mainboard/asus/p2b/Kconfig	(working copy)
@@ -2,6 +2,7 @@ 
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -29,6 +30,8 @@ 
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/asus/p2b/devicetree.cb
===================================================================
--- src/mainboard/asus/p2b/devicetree.cb	(revision 5500)
+++ src/mainboard/asus/p2b/devicetree.cb	(working copy)
@@ -39,7 +39,7 @@ 
           end
           device pnp 3f0.9 on		# GPIO 3
           end
-          device pnp 3f0.a on		# ACPI
+          device pnp 3f0.a off		# ACPI
           end
         end
       end
@@ -50,10 +50,10 @@ 
       register "ide1_enable" = "1"
       register "ide_legacy_enable" = "1"
       # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
     end
   end
 end
Index: src/mainboard/asus/p2b/acpi_tables.c
===================================================================
--- src/mainboard/asus/p2b/acpi_tables.c	(revision 0)
+++ src/mainboard/asus/p2b/acpi_tables.c	(revision 0)
@@ -0,0 +1,145 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by 
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Based on src/mainboard/asus/a8v-e_se/acpi_tables.c */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+/*
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h
+	if (!dev)
+		return current;
+*/
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapics(current);
+
+	/* IRQ9 ACPI active low. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT table. */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* We explicitly add these tables later on: */
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *)current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
+	dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/* If we want to use HPET timers Linux wants it in MADT. */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
Index: src/mainboard/asus/p2b/dsdt.asl
===================================================================
--- src/mainboard/asus/p2b/dsdt.asl	(revision 0)
+++ src/mainboard/asus/p2b/dsdt.asl	(revision 0)
@@ -0,0 +1,442 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Based on dsdt.asl from src/mainboard/asus/a8v-e_se */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	/* Define the main processor.*/
+	Scope (\_PR)
+	{
+		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+		Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
+	}
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * Any others would involve declaring the wake up methods.
+	 */
+
+	/* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
+	/*
+	000b / 0x0: soft off/suspend to disk (soff/std)			s5
+	001b / 0x1: suspend to ram (str)				s3
+	010b / 0x2: powered on suspend, context lost (poscl)		s1
+	011b / 0x3: powered on suspend, cpu context lost (posccl)	s2
+	100b / 0x4: powered on suspend, context maintained (pos)	s4
+	101b / 0x5: working (clock control)				s0
+	110b / 0x6: reserved
+	111b / 0x7: reserved
+	*/
+	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
+
+	OperationRegion (ARBI, SystemIO, 0x22, 0x1)
+
+	Field (ARBI, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x00),
+		ARDI, 1,
+	}
+
+	Method (_GTS, 1, NotSerialized)
+	{
+		If (LEqual (Arg0, 0x05))
+		{
+			Store (0x1, ARDI)
+			Sleep (0x10)
+		}
+	}
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+	{
+		/* Top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package (0x04) { 0x0001FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package (0x04) { 0x0001FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package (0x04) { 0x0001FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+				Package (0x04) { 0x0004FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package (0x04) { 0x0004FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package (0x04) { 0x0004FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package (0x04) { 0x0004FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+				Package (0x04) { 0x0009FFFF, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package (0x04) { 0x0009FFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package (0x04) { 0x0009FFFF, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package (0x04) { 0x0009FFFF, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+
+				Package (0x04) { 0x000AFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package (0x04) { 0x000AFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package (0x04) { 0x000AFFFF, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package (0x04) { 0x000AFFFF, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+
+				Package (0x04) { 0x000BFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package (0x04) { 0x000BFFFF, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package (0x04) { 0x000BFFFF, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package (0x04) { 0x000BFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+
+				Package (0x04) { 0x000CFFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package (0x04) { 0x000CFFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package (0x04) { 0x000CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package (0x04) { 0x000CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			})
+
+				// Intel LPC Bus Device  - 0:7.0
+
+				Device (LPCB)
+					{
+						Name(_ADR, 0x0040000)
+
+						OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+						Field (LPC0, AnyAcc, NoLock, Preserve)
+						{
+							Offset (0x40),
+							PMBS,	16,	// PMBASE
+							Offset (0x60),	// Interrupt Routing Registers
+							PRTA,	8,
+							PRTB,	8,
+							PRTC,	8,
+							PRTD,	8,
+						}
+
+					// this should go to some other file maybe 
+
+					Device (LNKA)
+					{
+						Name (_HID, EISAID("PNP0C0F"))
+						Name (_UID, 1)
+
+						// Disable method
+						Method (_DIS, 0, Serialized)
+						{
+							Store (0x80, PRTA)
+						}
+
+						// Possible Resource Settings for this Link
+						Name (_PRS, ResourceTemplate()
+						{
+							IRQ(Level, ActiveLow, Shared)
+								{ 9 }
+								//{ 10 }
+						})
+
+						// Current Resource Settings for this link
+						Method (_CRS, 0, Serialized)
+						{
+							Name (RTLA, ResourceTemplate()
+							{
+								IRQ(Level, ActiveLow, Shared) {}
+							})
+							CreateWordField(RTLA, 1, IRQ0)
+
+							// Clear the WordField
+							Store (Zero, IRQ0)
+
+							// Set the bit from PRTA
+							ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+							Return (RTLA)
+						}
+
+						// Set Resource Setting for this IRQ link
+						Method (_SRS, 1, Serialized)
+						{
+							CreateWordField(Arg0, 1, IRQ0)
+
+							// Which bit is set?
+							FindSetRightBit(IRQ0, Local0)
+
+							Decrement(Local0)
+							Store(Local0, PRTA)
+						}
+
+						// Status
+						Method (_STA, 0, Serialized)
+						{
+							If(And(PRTA, 0x80)) {
+								Return (0x9)
+							} Else {
+								Return (0xb)
+							}
+						}
+					} // LNKA
+
+					Device (LNKB)
+					{
+						Name (_HID, EISAID("PNP0C0F"))
+						Name (_UID, 2)
+
+						// Disable method
+						Method (_DIS, 0, Serialized)
+						{
+							Store (0x80, PRTB)
+						}
+
+						// Possible Resource Settings for this Link
+						Name (_PRS, ResourceTemplate()
+						{
+							IRQ(Level, ActiveLow, Shared)
+								{ 9 }
+								//{ 11 }
+						})
+
+						// Current Resource Settings for this link
+						Method (_CRS, 0, Serialized)
+						{
+							Name (RTLB, ResourceTemplate()
+							{
+								IRQ(Level, ActiveLow, Shared) {}
+							})
+							CreateWordField(RTLB, 1, IRQ0)
+
+							// Clear the WordField
+							Store (Zero, IRQ0)
+
+							// Set the bit from PRTB
+							ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+							Return (RTLB)
+						}
+
+						// Set Resource Setting for this IRQ link
+						Method (_SRS, 1, Serialized)
+						{
+							CreateWordField(Arg0, 1, IRQ0)
+
+							// Which bit is set?
+							FindSetRightBit(IRQ0, Local0)
+
+							Decrement(Local0)
+							Store(Local0, PRTB)
+						}
+
+						// Status
+						Method (_STA, 0, Serialized)
+						{
+							If(And(PRTB, 0x80)) {
+								Return (0x9)
+							} Else {
+								Return (0xb)
+							}
+						}
+					} // LNKB
+
+					Device (LNKC)
+					{
+						Name (_HID, EISAID("PNP0C0F"))
+						Name (_UID, 3)
+
+						// Disable method
+						Method (_DIS, 0, Serialized)
+						{
+							Store (0x80, PRTC)
+						}
+
+						// Possible Resource Settings for this Link
+						Name (_PRS, ResourceTemplate()
+						{
+							IRQ(Level, ActiveLow, Shared)
+								{ 9 }
+								//{ 10 }
+						})
+
+						// Current Resource Settings for this link
+						Method (_CRS, 0, Serialized)
+						{
+							Name (RTLC, ResourceTemplate()
+							{
+								IRQ(Level, ActiveLow, Shared) {}
+							})
+							CreateWordField(RTLC, 1, IRQ0)
+
+							// Clear the WordField
+							Store (Zero, IRQ0)
+
+							// Set the bit from PRTC
+							ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+							Return (RTLC)
+						}
+
+						// Set Resource Setting for this IRQ link
+						Method (_SRS, 1, Serialized)
+						{
+							CreateWordField(Arg0, 1, IRQ0)
+
+							// Which bit is set?
+							FindSetRightBit(IRQ0, Local0)
+
+							Decrement(Local0)
+							Store(Local0, PRTC)
+						}
+
+						// Status
+						Method (_STA, 0, Serialized)
+						{
+							If(And(PRTC, 0x80)) {
+								Return (0x9)
+							} Else {
+								Return (0xb)
+							}
+						}
+					} // LNKC
+
+					Device (LNKD)
+					{
+						Name (_HID, EISAID("PNP0C0F"))
+						Name (_UID, 4)
+
+						// Disable method
+						Method (_DIS, 0, Serialized)
+						{
+							Store (0x80, PRTD)
+						}
+
+						// Possible Resource Settings for this Link
+						Name (_PRS, ResourceTemplate()
+						{
+							IRQ(Level, ActiveLow, Shared)
+								{ 9 }
+								//{ 11 }
+						})
+
+						// Current Resource Settings for this link
+						Method (_CRS, 0, Serialized)
+						{
+							Name (RTLD, ResourceTemplate()
+							{
+								IRQ(Level, ActiveLow, Shared) {}
+							})
+							CreateWordField(RTLD, 1, IRQ0)
+
+							// Clear the WordField
+							Store (Zero, IRQ0)
+
+							// Set the bit from PRTD
+							ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+							Return (RTLD)
+						}
+
+						// Set Resource Setting for this IRQ link
+						Method (_SRS, 1, Serialized)
+						{
+							CreateWordField(Arg0, 1, IRQ0)
+
+							// Which bit is set?
+							FindSetRightBit(IRQ0, Local0)
+
+							Decrement(Local0)
+							Store(Local0, PRTD)
+						}
+
+						// Status
+						Method (_STA, 0, Serialized)
+						{
+							If(And(PRTD, 0x80)) {
+								Return (0x9)
+							} Else {
+								Return (0xb)
+							}
+						}
+					} // LNKD
+				} // LPCB
+
+			Device (ISA) {
+				Name (_ADR, 0x00110000)
+
+				/* PS/2 keyboard (seems to be important for WinXP install) */
+				Device (KBD)
+				{
+					Name (_HID, EisaId ("PNP0303"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+							IRQNoFlags () {1}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 mouse */
+				Device (MOU)
+				{
+					Name (_HID, EisaId ("PNP0F13"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+						     IRQNoFlags () {12}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 floppy controller */
+				Device (FDC0)
+				{
+					Name (_HID, EisaId ("PNP0700"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BUF0, ResourceTemplate () {
+							IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+							IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+							IRQNoFlags () {6}
+							DMA (Compatibility, NotBusMaster, Transfer8) {2}
+						})
+						Return (BUF0)
+					}
+				}
+			}
+		}
+
+	}
+}
Index: src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- src/northbridge/intel/i440bx/northbridge.c	(revision 5500)
+++ src/northbridge/intel/i440bx/northbridge.c	(working copy)
@@ -1,3 +1,23 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
@@ -15,7 +35,10 @@ 
 
 static void northbridge_init(device_t dev)
 {
+	u8 reg8; // as suggested by rudolf/ruik
 	printk(BIOS_SPEW, "Northbridge Init\n");
+	reg8 = pci_read_config16(dev, 0x7a); // as suggested by rudolf/ruik
+	pci_write_config8(dev, 0x7a, reg8 | 0x40); // as suggested by rudolf/ruik
 }
 
 static struct device_operations northbridge_operations = {