Patchwork Patch for enableing 440BX NB to use large memory modules

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Submitter Anders Jenbo
Date 2010-04-26 01:01:17
Message ID <1272243677.9444.14.camel@anders-laptop>
Download mbox | patch
Permalink /patch/1269/
State Superseded, archived
Headers show

Comments

Anders Jenbo - 2010-04-26 01:01:17
440BX can partially use memory larger then what is supported by seeing
them as being a max size supported module.

Single sided 512MB (what I used to test), becomes a 128MB.
A asymmetric 384MB double sided modules, with 256MB on one side and
128MB on the other. Becomes two sides with 128MB (a 256MB module).
This is also enabled in at least some BIOSs (GA-BXC).

The patch also cleans up some whitespace.

Signed-off-by: Anders Jenbo <anders@jenbo.dk>
---

Forgot to attach the actual patch...

Anders Jenbo
Paul Menzel - 2010-04-26 08:07:44
Am Montag, den 26.04.2010, 03:01 +0200 schrieb Anders Jenbo:
> 440BX can partially use memory larger then what is supported by seeing
> them as being a max size supported module.
> 
> Single sided 512MB (what I used to test), becomes a 128MB.
> A asymmetric 384MB double sided modules, with 256MB on one side and
> 128MB on the other. Becomes two sides with 128MB (a 256MB module).
> This is also enabled in at least some BIOSs (GA-BXC).

Interesting. Maybe add a link to the data sheet and tell what page this
is described on.

I have no way to test or the knowledge to acknowledge this patch. :( I
found some typos in the comments.

Maybe you can also add full stops (.) at the end of sentences.

> The patch also cleans up some whitespace.

This surely make it harder to review in the MUA. You have to apply the
patch and tell diff to ignore whitespace changes to make it easier to
review.

> Index: src/northbridge/intel/i440bx/raminit.c
> ===================================================================
> --- src/northbridge/intel/i440bx/raminit.c      (revision 5496)
> +++ src/northbridge/intel/i440bx/raminit.c      (working copy)

[…]

> +       /* It is posible to partialy use larger then supported modeuls by

s/posible/possible/
s/partialy/partially/
s/modeuls/modules/

> +        * setting them to a supported size.
> +        */
> +       if(sz.side1 > 128) {
> +               PRINT_DEBUG("Side1 was 0x");
> +               PRINT_DEBUG_HEX16(sz.side1);
> +               PRINT_DEBUG(" but only 128MB will be used\n");
> +               sz.side1 = 128;
> +
> +               if(sz.side2 > 128) {
> +                       PRINT_DEBUG("Side2 was 0x");
> +                       PRINT_DEBUG_HEX16(sz.side2);
> +                       PRINT_DEBUG(" but only 128MB will be used\n");
> +                       sz.side2 = 128;
> +               }
> +       }
> +
>         return sz;
>  }
>  /*
> @@ -724,15 +741,15 @@
>  
>                         PRINT_DEBUG("Found ");
>                         if (value == SPD_MEMORY_TYPE_EDO) {
> -                               edosd |= 0x02; 
> -                       } else if (value == SPD_MEMORY_TYPE_SDRAM) { 
> -                               edosd |= 0x04; 
> +                               edosd |= 0x02;
> +                       } else if (value == SPD_MEMORY_TYPE_SDRAM) {
> +                               edosd |= 0x04;
>                         }
>                         PRINT_DEBUG("DIMM in slot ");
>                         PRINT_DEBUG_HEX8(i);
>                         PRINT_DEBUG("\n");
>  
> -                       if (edosd == 0x06) { 
> +                       if (edosd == 0x06) {
>                                 print_err("Mixing EDO/SDRAM unsupported!\n");
>                                 die("HALT\n");
>                         }
> @@ -752,7 +769,7 @@
>  
>                         /* Data width */
>                         width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
> -                       
> +
>                         /* Exclude error checking data width from page size calculations */
>                         if (ecc) {
>                                 value = spd_read_byte(device,
> @@ -792,6 +809,12 @@
>                                         dra = 0x1; /* 4KB */
>                                 } else if (dra == 8) {
>                                         dra = 0x2; /* 8KB */
> +                               } else if (dra >= 16) {
> +                                       /* Page size larger then supported are
> +                                        * set to 8KB to use module partialy.
> +                                        */

s/size/sizes/
s/partialy/partially/


Thanks,

Paul
Stefan Reinauer - 2010-04-26 12:16:00
On 4/26/10 3:01 AM, Anders Jenbo wrote:
> 440BX can partially use memory larger then what is supported by seeing
> them as being a max size supported module.
>
> Single sided 512MB (what I used to test), becomes a 128MB.
> A asymmetric 384MB double sided modules, with 256MB on one side and
> 128MB on the other. Becomes two sides with 128MB (a 256MB module).
> This is also enabled in at least some BIOSs (GA-BXC).
>
> The patch also cleans up some whitespace.
>
> Signed-off-by: Anders Jenbo <anders@jenbo.dk>
>   
I like this...  no hardware to test though...

Acked-by: Stefan Reinauer <stepan@coresystems.de>

Patch

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(revision 5496)
+++ src/northbridge/intel/i440bx/raminit.c	(working copy)
@@ -210,7 +210,7 @@ 
 	 * 0x60 - 0x67
 	 *
 	 * An array of 8 byte registers, which hold the ending memory address
-	 * assigned to each pair of DIMMs, in 8MB granularity.   
+	 * assigned to each pair of DIMMs, in 8MB granularity.
 	 *
 	 * 0x60 DRB0 = Total memory in row0 (in 8 MB)
 	 * 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
@@ -433,13 +433,13 @@ 
 static void set_dram_buffer_strength(void)
 {
 	/* To give some breathing room for romcc,
-	 * mbsc0 doubles as drb 
+	 * mbsc0 doubles as drb
 	 * mbsc1 doubles as drb1
 	 * mbfs0 doubles as i and reg
 	 */
 	uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;
 
-	/* Tally how many rows between rows 0-3 and rows 4-7 are populated. 
+	/* Tally how many rows between rows 0-3 and rows 4-7 are populated.
 	 * This determines how to program MBFS and MBSC.
 	 */
 	uint8_t dimm03 = 0;
@@ -527,7 +527,7 @@ 
 	 * Therefore it assumes a board with 4 slots, and will need testing
 	 * on boards with 3 DIMM slots.
 	 */
-	 
+
 	mbsc0 = 0x80;
 	mbsc1 = 0x2a;
 	mbfs2 = 0x1f;
@@ -542,36 +542,36 @@ 
 		mbsc4 = 0x0a;
 		mbfs0 = 0x84;
 	}
-	
-	if (dimm03 > 2) { 
-		mbsc4 = mbsc4 | 0x80; 
+
+	if (dimm03 > 2) {
+		mbsc4 = mbsc4 | 0x80;
 		mbsc1 = mbsc1 | 0x28;
 		mbfs2 = mbfs2 | 0x40;
 		mbfs0 = mbfs0 | 0x60;
-	} else { 
-		mbsc4 = mbsc4 | 0xc0; 
+	} else {
+		mbsc4 = mbsc4 | 0xc0;
 		if (fsb == 100) {
 			mbsc1 = mbsc1 | 0x3c;
 		}
-	}	
-	if (dimm47 > 2) { 
-		mbsc4 = mbsc4 | 0x20; 
-		mbsc1 = mbsc1 | 0x02; 
+	}
+	if (dimm47 > 2) {
+		mbsc4 = mbsc4 | 0x20;
+		mbsc1 = mbsc1 | 0x02;
 		mbsc0 = mbsc0 | 0x80;
 		mbfs2 = mbfs2 | 0x20;
 		mbfs0 = mbfs0 | 0x18;
-	} else { 
+	} else {
 		mbsc4 = mbsc4 | 0x30;
 		if (fsb == 100) {
-			mbsc1 = mbsc1 | 0x03; 
+			mbsc1 = mbsc1 | 0x03;
 			mbsc0 = mbsc0 | 0xc0;
 		}
 	}
-	if ((dimm03 + dimm47) > 4) { 
+	if ((dimm03 + dimm47) > 4) {
 		mbsc0 = mbsc0 | 0x30;
 		mbfs0 = mbfs0 | 0x02;
-	} else { 
-		mbsc0 = mbsc0 | 0x2c; 
+	} else {
+		mbsc0 = mbsc0 | 0x2c;
 	}
 
 	pci_write_config8(NB, MBSC + 0, mbsc0);
@@ -694,6 +694,23 @@ 
 	sz.side1 *= 4;
 	sz.side2 *= 4;
 
+	/* It is posible to partialy use larger then supported modeuls by
+	 * setting them to a supported size.
+	 */
+	if(sz.side1 > 128) {
+		PRINT_DEBUG("Side1 was 0x");
+		PRINT_DEBUG_HEX16(sz.side1);
+		PRINT_DEBUG(" but only 128MB will be used\n");
+		sz.side1 = 128;
+
+		if(sz.side2 > 128) {
+			PRINT_DEBUG("Side2 was 0x");
+			PRINT_DEBUG_HEX16(sz.side2);
+			PRINT_DEBUG(" but only 128MB will be used\n");
+			sz.side2 = 128;
+		}
+	}
+
 	return sz;
 }
 /*
@@ -724,15 +741,15 @@ 
 
 			PRINT_DEBUG("Found ");
 			if (value == SPD_MEMORY_TYPE_EDO) {
-				edosd |= 0x02; 
-			} else if (value == SPD_MEMORY_TYPE_SDRAM) { 
-				edosd |= 0x04; 
+				edosd |= 0x02;
+			} else if (value == SPD_MEMORY_TYPE_SDRAM) {
+				edosd |= 0x04;
 			}
 			PRINT_DEBUG("DIMM in slot ");
 			PRINT_DEBUG_HEX8(i);
 			PRINT_DEBUG("\n");
 
-			if (edosd == 0x06) { 
+			if (edosd == 0x06) {
 				print_err("Mixing EDO/SDRAM unsupported!\n");
 				die("HALT\n");
 			}
@@ -752,7 +769,7 @@ 
 
 			/* Data width */
 			width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
-			
+
 			/* Exclude error checking data width from page size calculations */
 			if (ecc) {
 				value = spd_read_byte(device,
@@ -792,6 +809,12 @@ 
 					dra = 0x1; /* 4KB */
 				} else if (dra == 8) {
 					dra = 0x2; /* 8KB */
+				} else if (dra >= 16) {
+					/* Page size larger then supported are
+					 * set to 8KB to use module partialy.
+					 */
+					PRINT_DEBUG("Page size forced to 8KB\n");
+					dra = 0x2; /* 8KB */
 				} else {
 					dra = -1;
 				}
@@ -808,6 +831,10 @@ 
 					dra = 0x05; /* 4KB */
 				} else if (dra == 8) {
 					dra = 0x0a; /* 8KB */
+				} else if (dra >= 16) {
+					/* Ditto */
+					PRINT_DEBUG("Page size forced to 8KB\n");
+					dra = 0x0a; /* 8KB */
 				} else {
 					dra = -1;
 				}
@@ -826,7 +853,7 @@ 
 			/*
 			 * 440BX supports asymmetrical dual-sided DIMMs,
 			 * but can't handle DIMMs smaller than 8MB per
-			 * side or larger than 128MB per side.
+			 * side.
 			 */
 			struct dimm_size sz = spd_get_dimm_size(device);
 			if ((sz.side1 < 8)) {
@@ -834,11 +861,6 @@ 
 					  "are not supported on this NB.\n");
 				die("HALT\n");
 			}
-			if ((sz.side1 > 128)) {
-				print_err("DIMMs > 128MB per side\n"
-					   "are not supported on this NB\n");
-				die("HALT\n");
-			}
 
 			/* Divide size by 8 to set up the DRB registers. */
 			drb += (sz.side1 / 8);