Patchwork [Review,Request,1/2] Prepare for Clevo D900T

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Submitter Pat Erley
Date 2010-04-29 21:36:29
Message ID <1272576990-24995-2-git-send-email-pat-lkml@erley.org>
Download mbox | patch
Permalink /patch/1280/
State New
Headers show

Comments

Pat Erley - 2010-04-29 21:36:29
This adds a preliminary clevo/d900t target for me to use as I
    add new support for:

     * ICH6
     * i915P
     * Socket 775
     * New P4 Procs
     * NSC PC87393F Super I/O

    So that successful build can be shown with each additional chip
    addition.

    Based on intel/d945gclf

Signed-off-by: Pat Erley <pat-lkml@erley.org>
---
 src/mainboard/Kconfig                   |    8 +
 src/mainboard/clevo/Kconfig             |   28 +++
 src/mainboard/clevo/d900t/Kconfig       |   98 +++++++++
 src/mainboard/clevo/d900t/Makefile.inc  |   19 ++
 src/mainboard/clevo/d900t/chip.h        |   23 ++
 src/mainboard/clevo/d900t/cmos.layout   |  142 +++++++++++++
 src/mainboard/clevo/d900t/devicetree.cb |  108 ++++++++++
 src/mainboard/clevo/d900t/mainboard.c   |   34 +++
 src/mainboard/clevo/d900t/romstage.c    |  344 +++++++++++++++++++++++++++++++
 9 files changed, 804 insertions(+), 0 deletions(-)
 create mode 100644 src/mainboard/clevo/Kconfig
 create mode 100644 src/mainboard/clevo/d900t/Kconfig
 create mode 100644 src/mainboard/clevo/d900t/Makefile.inc
 create mode 100644 src/mainboard/clevo/d900t/chip.h
 create mode 100644 src/mainboard/clevo/d900t/cmos.layout
 create mode 100644 src/mainboard/clevo/d900t/devicetree.cb
 create mode 100644 src/mainboard/clevo/d900t/mainboard.c
 create mode 100644 src/mainboard/clevo/d900t/romstage.c

Patch

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index d989ffd..c228042 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -32,6 +32,8 @@  config VENDOR_BIOSTAR
 	bool "Biostar"
 config VENDOR_BROADCOM
 	bool "Broadcom"
+config VENDOR_CLEVO
+	bool "Clevo"
 config VENDOR_COMPAQ
 	bool "Compaq"
 config VENDOR_DELL
@@ -175,6 +177,11 @@  config MAINBOARD_VENDOR
 
 config MAINBOARD_VENDOR
 	string
+	default "Clevo"
+	depends on VENDOR_CLEVO
+
+config MAINBOARD_VENDOR
+	string
 	default "Compaq"
 	depends on VENDOR_COMPAQ
 
@@ -387,6 +394,7 @@  source "src/mainboard/azza/Kconfig"
 source "src/mainboard/bcom/Kconfig"
 source "src/mainboard/biostar/Kconfig"
 source "src/mainboard/broadcom/Kconfig"
+source "src/mainboard/clevo/Kconfig"
 source "src/mainboard/compaq/Kconfig"
 source "src/mainboard/dell/Kconfig"
 source "src/mainboard/digitallogic/Kconfig"
diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig
new file mode 100644
index 0000000..d662e7f
--- /dev/null
+++ b/src/mainboard/clevo/Kconfig
@@ -0,0 +1,28 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_CLEVO
+
+source "src/mainboard/clevo/d900t/Kconfig"
+
+endchoice
+
diff --git a/src/mainboard/clevo/d900t/Kconfig b/src/mainboard/clevo/d900t/Kconfig
new file mode 100644
index 0000000..50e272f
--- /dev/null
+++ b/src/mainboard/clevo/d900t/Kconfig
@@ -0,0 +1,98 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_CLEVO_D900T
+	bool "D900T"
+	select ARCH_X86
+#	select CPU_INTEL_MODEL_F4X
+#	select CPU_INTEL_SOCKET_LGA775
+#	select CPU_INTEL_ATOM_230
+#	select CPU_INTEL_SOCKET_441
+#	select NORTHBRIDGE_INTEL_I945
+#	select SOUTHBRIDGE_INTEL_I82801GX
+#	select SUPERIO_SMSC_LPC47M15X
+#	select BOARD_HAS_FADT
+#	select GENERATE_ACPI_TABLES
+#	select GENERATE_PIRQ_TABLE
+#	select GENERATE_MP_TABLE
+#	select HAVE_HARD_RESET
+#	select HAVE_PIRQ_TABLE
+#	select HAVE_MP_TABLE
+#	select HAVE_ACPI_TABLES
+#	select HAVE_ACPI_RESUME
+#	select HAVE_MAINBOARD_RESOURCES
+#	select MMCONF_SUPPORT
+#	select USE_PRINTK_IN_CAR
+#	select HAVE_ACPI_TABLES
+#	select HAVE_SMI_HANDLER
+	select BOARD_ROMSIZE_KB_512
+#	select USE_DCACHE_RAM
+#	select GFXUMA
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default clevo/d900t
+	depends on BOARD_CLEVO_D900T
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffdf8000
+#	depends on BOARD_CLEVO_D900T
+
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_CLEVO_D900T
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "D900T"
+	depends on BOARD_CLEVO_D900T
+
+#config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+#	hex
+#	default 0x464C
+#	depends on BOARD_CLEV_D900T
+
+#config MMCONF_BASE_ADDRESS
+#	hex
+#	default 0xf0000000
+#	depends on BOARD_CLEVO_D900T
+
+#config IRQ_SLOT_COUNT
+#	int
+#	default 18
+#	depends on BOARD_CLEVO_D900T
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_CLEVO_D900T
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+	depends on BOARD_CLEVO_D900T
+
+#config HAVE_ACPI_SLIC
+#	bool
+#	default n
+#	depends on BOARD_CLEVO_D900T
+
diff --git a/src/mainboard/clevo/d900t/Makefile.inc b/src/mainboard/clevo/d900t/Makefile.inc
new file mode 100644
index 0000000..a62408a
--- /dev/null
+++ b/src/mainboard/clevo/d900t/Makefile.inc
@@ -0,0 +1,19 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
diff --git a/src/mainboard/clevo/d900t/chip.h b/src/mainboard/clevo/d900t/chip.h
new file mode 100644
index 0000000..4e1432d
--- /dev/null
+++ b/src/mainboard/clevo/d900t/chip.h
@@ -0,0 +1,23 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {
+	int nothing;
+};
diff --git a/src/mainboard/clevo/d900t/cmos.layout b/src/mainboard/clevo/d900t/cmos.layout
new file mode 100644
index 0000000..9997584
--- /dev/null
+++ b/src/mainboard/clevo/d900t/cmos.layout
@@ -0,0 +1,142 @@ 
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+#928         80       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/clevo/d900t/devicetree.cb b/src/mainboard/clevo/d900t/devicetree.cb
new file mode 100644
index 0000000..6b64ebf
--- /dev/null
+++ b/src/mainboard/clevo/d900t/devicetree.cb
@@ -0,0 +1,108 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#chip northbridge/intel/i945
+#
+#       device apic_cluster 0 on
+#                chip cpu/intel/socket_LGA775
+#                        device apic 0 on end
+#                end
+#        end
+#
+#        device pci_domain 0 on
+#                device pci 00.0 on end # host bridge
+#		device pci 01.0 off end # i945 PCIe root port
+#		device pci 02.0 on end # vga controller
+#		device pci 02.1 on end # display controller
+#
+#                chip southbridge/intel/i82801gx
+#			register "pirqa_routing" = "0x05"
+#			register "pirqb_routing" = "0x07"
+#			register "pirqc_routing" = "0x05"
+#			register "pirqd_routing" = "0x07"
+#			register "pirqe_routing" = "0x80"
+#			register "pirqf_routing" = "0x80"
+#			register "pirqg_routing" = "0x80"
+#			register "pirqh_routing" = "0x06"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+#			register "gpi13_routing" = "1"
+#			register "gpe0_en" = "0x20000601"
+
+#                        register "ide_legacy_combined" = "0x1"
+#                        register "ide_enable_primary" = "0x1"
+#                        register "ide_enable_secondary" = "0x0"
+#                        register "sata_ahci" = "0x0"
+
+#                	device pci 1b.0 on end # High Definition Audio
+#                	device pci 1c.0 on end # PCIe
+#                	device pci 1c.1 on end # PCIe
+#                	device pci 1c.2 on end # PCIe
+			#device pci 1c.3 off end # PCIe port 4
+			#device pci 1c.4 off end # PCIe port 5
+			#device pci 1c.5 off end # PCIe port 6
+#                	device pci 1d.0 on end # USB UHCI
+#                	device pci 1d.1 on end # USB UHCI
+#                	device pci 1d.2 on end # USB UHCI
+#                	device pci 1d.3 on end # USB UHCI
+#                	device pci 1d.7 on end # USB2 EHCI
+#                	device pci 1e.0 on end # PCI bridge
+			#device pci 1e.2 off end # AC'97 Audio
+			#device pci 1e.3 off end # AC'97 Modem
+#                        device pci 1f.0 on # LPC bridge
+#                                chip superio/smsc/lpc47m15x
+#					device pnp 2e.0 off		# Floppy
+#					end
+#					device pnp 2e.3 off		# Parport
+#					end
+#                                        device pnp 2e.4 on
+#                                                 io 0x60 = 0x3f8
+#                                                irq 0x70 = 4
+#                                        end
+#                                        device pnp 2e.5 on
+#                                                 io 0x60 = 0x2f8
+#                                                irq 0x70 = 3
+#						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
+#                                        end
+#					device pnp 2e.7 on		# Keyboard+Mouse
+#						 io 0x60 = 0x60
+#						 io 0x62 = 0x64
+#						irq 0x70 = 1
+#						irq 0x72 = 12
+#						irq 0xf0 = 0x82		# HW accel A20.
+#					end
+#					device pnp 2e.8 on		# GAME
+						# all default
+#					end
+#					device pnp 2e.a on		# PME
+#					end
+#					device pnp 2e.b on		# MPU
+#					end
+#                                end
+#                        end
+			#device pci 1f.1 off end # IDE
+#                        device pci 1f.2 on end  # SATA
+#                        device pci 1f.3 on end  # SMBus
+			#device pci 1f.4 off end # Realtek ID Codec
+#                end
+#        end
+end
diff --git a/src/mainboard/clevo/d900t/mainboard.c b/src/mainboard/clevo/d900t/mainboard.c
new file mode 100644
index 0000000..fc2453a
--- /dev/null
+++ b/src/mainboard/clevo/d900t/mainboard.c
@@ -0,0 +1,34 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <console/console.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
+#include "chip.h"
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return 0; //add_northbridge_resources(mem);
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Clevo D900T Mainboard")
+};
+
diff --git a/src/mainboard/clevo/d900t/romstage.c b/src/mainboard/clevo/d900t/romstage.c
new file mode 100644
index 0000000..290eadd
--- /dev/null
+++ b/src/mainboard/clevo/d900t/romstage.c
@@ -0,0 +1,344 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+/* Configuration of the i945 driver */
+#if 0
+#define CHIPSET_I945GC 1
+#define CHANNEL_XOR_RANDOMIZATION 1
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#if 0
+#include "superio/smsc/lpc47m15x/lpc47m15x.h"
+
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include <console/console.h>
+#include "pc80/serial.c"
+#include "console/console.c"
+#include <cpu/x86/bist.h>
+
+#if CONFIG_USBDEBUG_DIRECT
+#define DBGP_DEFAULT 1
+#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
+
+#include "northbridge/intel/i945/udelay.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
+#include "southbridge/intel/i82801gx/i82801gx.h"
+static void setup_ich7_gpios(void)
+{
+	/* TODO: This is highly board specific and should be moved */
+	printk(BIOS_DEBUG, " GPIOS...");
+	/* General Registers */
+	outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00040000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000000ff, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x000000bf, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
+}
+
+#include "northbridge/intel/i945/early_init.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i945/raminit.h"
+#include "northbridge/intel/i945/raminit.c"
+#include "northbridge/intel/i945/errata.c"
+#include "northbridge/intel/i945/debug.c"
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// Set COM1/COM2 decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	// Enable COM1
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
+	// Enable SuperIO Power Management Events
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
+}
+
+/* This box has two superios, so enabling serial becomes slightly excessive.
+ * We disable a lot of stuff to make sure that there are no conflicts between
+ * the two. Also set up the GPIOs from the beginning. This is the "no schematic
+ * but safe anyways" method.
+ */
+static void early_superio_config_lpc47m15x(void)
+{
+	device_t dev;
+
+	dev=PNP_DEV(0x2e, LPC47M15X_SP1);
+	pnp_enter_conf_state(dev);
+
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
+	pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
+	pnp_set_enable(dev, 1);
+
+	/* Enable SuperIO PM */
+	dev=PNP_DEV(0x2e, LPC47M15X_PME);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, 0x680);
+	pnp_set_enable(dev, 1);
+
+	pnp_exit_conf_state(dev);
+}
+
+static void rcba_config(void)
+{
+	/* Set up virtual channel 0 */
+	//RCBA32(0x0014) = 0x80000001;
+	//RCBA32(0x001c) = 0x03128010;
+
+	/* Device 1f interrupt pin register */
+	RCBA32(0x3100) = 0x00042210;
+	/* Device 1d interrupt pin register */
+	RCBA32(0x310c) = 0x00214321;
+
+	/* dev irq route register */
+	RCBA16(0x3140) = 0x0132;
+	RCBA16(0x3142) = 0x0146;
+	RCBA16(0x3144) = 0x0237;
+	RCBA16(0x3146) = 0x3201;
+	RCBA16(0x3148) = 0x0146;
+
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable unused devices */
+	//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
+	// RCBA32(0x3418) |= (1 << 0); // Required.
+	// FIXME look me up!
+	RCBA32(0x3418) = 0x003204e1;
+
+	/* Enable PCIe Root Port Clock Gate */
+	// RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030549;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+#include <cbmem.h>
+
+// Now, this needs to be included because it relies on the symbol
+// __PRE_RAM__ being set during CAR stage (in order to compile the
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
+//
+#include "lib/cbmem.c"
+
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+
+	if (bist == 0) {
+		enable_lapic();
+	}
+
+	ich7_enable_lpc();
+	early_superio_config_lpc47m15x();
+
+	/* Set up the console */
+	uart_init();
+
+#if CONFIG_USBDEBUG_DIRECT
+	i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected.\n");
+		boot_mode = 1;
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+        /* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+
+	sdram_initialize(boot_mode);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if defined(DEBUG_RAM_SETUP)
+	sdram_dump_mchbar_registers();
+#endif
+
+	{
+		/* This will not work if TSEG is in place! */
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
+		ram_check(0x00000000, 0x000a0000);
+		//ram_check(0x00100000, tom);
+	}
+#endif
+#endif
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Start address of high memory tables */
+	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	}
+#endif
+}
+#endif