===================================================================
@@ -100,6 +100,8 @@
bool "VIA"
config VENDOR_WINENT
bool "Win Enterprises"
+config VENDOR_WYSE
+ bool "Wyse"
endchoice
@@ -373,6 +375,16 @@
default "Win Enterprise"
depends on VENDOR_WINENT
+config MAINBOARD_VENDOR
+ string
+ default "Wyse"
+ depends on VENDOR_WYSE
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x102d
+ depends on VENDOR_WYSE
+
source "src/mainboard/a-trend/Kconfig"
source "src/mainboard/abit/Kconfig"
source "src/mainboard/advantech/Kconfig"
@@ -421,6 +433,7 @@
source "src/mainboard/tyan/Kconfig"
source "src/mainboard/via/Kconfig"
source "src/mainboard/winent/Kconfig"
+source "src/mainboard/wyse/Kconfig"
config BOARD_ROMSIZE_KB_128
bool
===================================================================
@@ -0,0 +1,8 @@
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_WYSE
+
+source "src/mainboard/wyse/s50/Kconfig"
+
+endchoice
+
===================================================================
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config BOARD_WYSE_S50
+ bool "S50"
+ select ARCH_X86
+ select CPU_AMD_GX2
+ select NORTHBRIDGE_AMD_GX2
+ select SOUTHBRIDGE_AMD_CS5536
+ select ROMCC
+ select UDELAY_TSC
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+ string
+ default wyse/s50
+ depends on BOARD_WYSE_S50
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "s50"
+ depends on BOARD_WYSE_S50
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_WYSE_S50
+
+config IRQ_SLOT_COUNT
+ int
+ default 3
+ depends on BOARD_WYSE_S50
===================================================================
@@ -0,0 +1,167 @@
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "console/console.c"
+#include "lib/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/gx2def.h>
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/gx2/raminit.h"
+
+static inline unsigned int ctz(unsigned int n)
+{
+ int zeros;
+
+ n = (n ^ (n - 1)) >> 1;
+ for (zeros = 0; n; zeros++)
+ {
+ n >>= 1;
+ }
+ return zeros;
+}
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
+ * component Banks (byte 17) * module banks, side (byte 5) *
+ * width in bits (byte 6,7)
+ * = Density per side (byte 31) * number of sides (byte 5) */
+ /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
+ msr_t msr;
+ unsigned char module_banks, val;
+ uint16_t dimm_size;
+
+ msr = rdmsr(MC_CF07_DATA);
+
+ /* get module banks (sides) per dimm, SPD byte 5 */
+ module_banks = spd_read_byte(0xA0, 5);
+ if (module_banks < 1 || module_banks > 2)
+ print_err("Module banks per dimm\n");
+ module_banks >>= 1;
+ msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
+ msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
+
+ /* get component banks per module bank, SPD byte 17 */
+ val = spd_read_byte(0xA0, 17);
+ if (val < 2 || val > 4)
+ print_err("Component banks per module bank\n");
+ val >>= 2;
+ msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
+ msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
+
+ dimm_size = spd_read_byte(0xA0, 31);
+ dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
+ dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
+ /* Module Density * Module Banks */
+ dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
+ if (dimm_size != 0) {
+ dimm_size = ctz(dimm_size);
+ }
+ if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
+ print_err("Only support up to 512MB \n");
+ hlt();
+ }
+ msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
+
+ /* page size = 2^col address */
+ val = spd_read_byte(0xA0, 4);
+ val -= 7;
+ msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
+ msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
+
+ print_debug("computed msr.hi ");
+ print_debug_hex32(msr.hi);
+ print_debug("\n");
+
+ msr.lo = 0x00003400;
+ wrmsr(MC_CF07_DATA, msr);
+
+ msr = rdmsr(MC_CF8F_DATA);
+ msr.hi = 0x18000008;
+ msr.lo = 0x296332a3;
+ wrmsr(MC_CF8F_DATA, msr);
+
+}
+
+#include "northbridge/amd/gx2/raminit.c"
+#include "lib/generic_sdram.c"
+
+#include "northbridge/amd/gx2/pll_reset.c"
+#include "cpu/amd/model_gx2/cpureginit.c"
+#include "cpu/amd/model_gx2/syspreinit.c"
+
+static void msr_init(void)
+{
+ /* total physical memory */
+ __builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002);
+
+ /* traditional memory 0kB-512kB, 512kB-1MB */
+ __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
+ __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040);
+ __builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f);
+ __builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff);
+
+ __builtin_wrmsr(0x10000080, 0x3, 0x0);
+
+ __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
+ __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
+ __builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f);
+ __builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff);
+
+ __builtin_wrmsr(0x40000080, 0x1, 0x0);
+
+ __builtin_wrmsr(0x50002001, 0x27, 0x0);
+ __builtin_wrmsr(0x4c002001, 0x1, 0x0);
+
+ /* put code in northbridge[init].c here */
+}
+
+static void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl [] = {
+ {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* disable the power button */
+ outl(0x00, PMS_IO_BASE + 0x40);
+
+ cs5536_setup_onchipuart(1);
+
+ uart_init();
+ console_init();
+
+ pll_reset();
+
+ cpuRegInit();
+ print_err("done cpuRegInit\n");
+
+ sdram_initialize(1, memctrl);
+ print_err("ram setup done\n");
+
+ /* Check all of memory */
+ /*ram_check(0x00000000, 640*1024);*/
+ print_err("ram check done\n");
+}
+
===================================================================
@@ -0,0 +1,32 @@
+chip northbridge/amd/gx2
+ register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
+ device apic_cluster 0 on
+ chip cpu/amd/model_gx2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ device pci e.0 on end # Realtek 8139 LAN
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+end
+
===================================================================
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO@TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x0f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x100b, /* Vendor */
+ 0x2b, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xdc, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0},
+ {0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0},
+ {0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
===================================================================
@@ -0,0 +1,5 @@
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+ int nicirq;
+};
===================================================================
@@ -0,0 +1,12 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("WYSE S50 Mainboard")
+};
+
===================================================================
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Hi all, Attached patches add the Wyse S50 thin client to Coreboot. I have rev5446 and some older rev`s working here with different hacks but rev5484 and 5520 (and some i tested in between) are not working anymore. Linux gives the following error: "hda: lost interrupt" . Attached also the bootlogs from rev5446 and rev5520. Could somebody give me a hint (or even better a patch) i can try? Although the patches are probably not ready for inclusion: Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Thanks,Nils.