Patchwork Fix coreboot qemu RAM size detection

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Submitter Vladimir 'φ-coder/phcoder' Serbinenko
Date 2010-05-02 15:00:29
Message ID <4BDD938D.6020105@gmail.com>
Download mbox | patch
Permalink /patch/1284/
State Accepted
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Comments

Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM.
Fix attached. Tested from 16 MiB to 2047 MiB
Stefan Reinauer - 2010-05-02 15:51:46
On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM.
> Fix attached. Tested from 16 MiB to 2047 MiB
>
>   
Hi Vladimir,

please sign off your patch so we can commit it:

http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure


Thanks,
Stefan
Stefan Reinauer wrote:
> On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM.
>> Fix attached. Tested from 16 MiB to 2047 MiB
>>
>>   
> Hi Vladimir,
>
> please sign off your patch so we can commit it:
>
> http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
>
This patch is done by me based on info retrieved from
grub-as-qemu-firmware. The chunk which contained the needed info was 4
lines long. So it's not copyright-significant. Since this patch is small
I hereby give up my copyright on it and release it to public domain.
Signed-off-by: Valdimir 'φ-coder' Serbinenko <phcoder@gmail.com>
>
> Thanks,
> Stefan
Stefan Reinauer - 2010-05-03 16:24:26
On 5/2/10 6:23 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>>     
>>> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM.
>>> Fix attached. Tested from 16 MiB to 2047 MiB
>>>
>>>   
> Signed-off-by: Valdimir 'φ-coder' Serbinenko <phcoder@gmail.com>
>   
Thanks. Slightly simplified and committed as r5521
Stefan

Patch

=== modified file 'src/mainboard/emulation/qemu-x86/northbridge.c'
--- src/mainboard/emulation/qemu-x86/northbridge.c	2010-04-08 11:47:35 +0000
+++ src/mainboard/emulation/qemu-x86/northbridge.c	2010-05-02 14:57:46 +0000
@@ -53,42 +53,31 @@ 
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
+#define CMOS_ADDR_PORT 0x70
+#define CMOS_DATA_PORT 0x71
+#define HIGH_RAM_ADDR 0x35
+#define LOW_RAM_ADDR 0x34
+
 static void cpu_pci_domain_set_resources(device_t dev)
 {
-	static const uint8_t ramregs[] = {
-		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
-	};
 	device_t mc_dev;
 	uint32_t pci_tolm;
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
-		unsigned long tomk, tolmk;
-		unsigned char rambits;
-		int i, idx;
-
-		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
-			unsigned char reg;
-			reg = pci_read_config8(mc_dev, ramregs[i]);
-			/* these are ENDING addresses, not sizes.
-			 * if there is memory in this slot, then reg will be > rambits.
-			 * So we just take the max, that gives us total.
-			 * We take the highest one to cover for once and future coreboot
-			 * bugs. We warn about bugs.
-			 */
-			if (reg > rambits)
-				rambits = reg;
-			if (reg < rambits)
-				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
-					ramregs[i]);
-		}
-		if (rambits == 0) {
-			printk(BIOS_ERR, "RAM size config registers are empty; defaulting to 64 MBytes\n");
-			rambits = 8;
-		}
-		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
-		tomk = rambits*8*1024;
+		unsigned long tomk = 0, tolmk;
+		int idx;
+
+		outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT);
+		tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
+		outb (LOW_RAM_ADDR, CMOS_ADDR_PORT);
+		tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
+		tomk += 16 * 1024;
+
+		printk(BIOS_DEBUG,
+		       "I would set ram size to 0x%lx Kbytes (%lu MiB)\n",
+		       tomk, tomk / 1024);
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {