Patchwork PATCH: model_6bx CPUs can go in a lot of places

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Submitter Keith Hui
Date 2010-05-07 03:31:49
Message ID <q2ib72cdb061005062031p96799fb9r695ff6b6936b39e0@mail.gmail.com>
Download mbox | patch
Permalink /patch/1293/
State New
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Comments

Keith Hui - 2010-05-07 03:31:49
Hi all,

Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of
places, specifically Slot 1 and Socket 370. Ever since references to
them were removed from cpu/intel/model_6xx my coreboot would die when
initializing CPU with a "Unknown cpu" error. This patch fixes it by
adding references to model_6bx to cpu/intel/slot_1 and
cpu/intel/socket_PGA370. Also included are before and after boot logs
with relevant sections highlighted.

Before boot log: http://coreboot.pastebin.com/CGWgihaG
After boot log: http://coreboot.pastebin.com/GLgnpZT6

Signed-off-by: Keith Hui <buurin@gmail.com>

----- Begin patch -----

----- End patch -----
Joseph Smith - 2010-05-07 13:39:02
On Thu, 6 May 2010 23:31:49 -0400, Keith Hui <buurin@gmail.com> wrote:
> Hi all,
> 
> Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of
> places, specifically Slot 1 and Socket 370. Ever since references to
> them were removed from cpu/intel/model_6xx my coreboot would die when
> initializing CPU with a "Unknown cpu" error. This patch fixes it by
> adding references to model_6bx to cpu/intel/slot_1 and
> cpu/intel/socket_PGA370. Also included are before and after boot logs
> with relevant sections highlighted.
> 
> Before boot log: http://coreboot.pastebin.com/CGWgihaG
> After boot log: http://coreboot.pastebin.com/GLgnpZT6
> 
> Signed-off-by: Keith Hui <buurin@gmail.com>
> 
> ----- Begin patch -----
> Index: src/cpu/intel/slot_1/Makefile.inc
> ===================================================================
> --- src/cpu/intel/slot_1/Makefile.inc	(revision 5527)
> +++ src/cpu/intel/slot_1/Makefile.inc	(working copy)
> @@ -20,6 +20,7 @@
> 
>  obj-y += slot_1.o
>  subdirs-y += ../model_6xx
> +subdirs-y += ../model_6bx
>  subdirs-y += ../../x86/tsc
>  subdirs-y += ../../x86/mtrr
>  subdirs-y += ../../x86/lapic
> Index: src/cpu/intel/socket_PGA370/Makefile.inc
> ===================================================================
> --- src/cpu/intel/socket_PGA370/Makefile.inc	(revision 5527)
> +++ src/cpu/intel/socket_PGA370/Makefile.inc	(working copy)
> @@ -20,6 +20,7 @@
> 
>  obj-y += socket_PGA370.o
>  subdirs-y += ../model_6xx
> +subdirs-y += ../model_6bx
>  subdirs-y += ../../x86/tsc
>  subdirs-y += ../../x86/mtrr
>  subdirs-y += ../../x86/lapic
> 
> ----- End patch -----
> 
Hello Keith,
I kind of saw this coming. That is why I left the 6bx's in model_6xx. The
new model_6bx is intended for CAR, so I don't know how well it will work
with romcc. My advice is to either get CAR running on your board, or we put
back the 6bx's in model_6xx for the interim.
Keith Hui - 2010-05-07 17:00:37
I think I should get CAR running. But CAR is not quite developed for
the rest of the 6xx family.

If you look at the boot log you'll see that it got through to SeaBIOS
just fine. My coreboot is still on romcc.

What are the steps needed to enable CAR on a board?

Thanks
Keith

On 5/7/10, Joseph Smith <joe@settoplinux.org> wrote:
>
>
>
> On Thu, 6 May 2010 23:31:49 -0400, Keith Hui <buurin@gmail.com> wrote:
>> Hi all,
>>
>> Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of
>> places, specifically Slot 1 and Socket 370. Ever since references to
>> them were removed from cpu/intel/model_6xx my coreboot would die when
>> initializing CPU with a "Unknown cpu" error. This patch fixes it by
>> adding references to model_6bx to cpu/intel/slot_1 and
>> cpu/intel/socket_PGA370. Also included are before and after boot logs
>> with relevant sections highlighted.
>>
>> Before boot log: http://coreboot.pastebin.com/CGWgihaG
>> After boot log: http://coreboot.pastebin.com/GLgnpZT6
>>
>> Signed-off-by: Keith Hui <buurin@gmail.com>
>>
>> ----- Begin patch -----
>> Index: src/cpu/intel/slot_1/Makefile.inc
>> ===================================================================
>> --- src/cpu/intel/slot_1/Makefile.inc	(revision 5527)
>> +++ src/cpu/intel/slot_1/Makefile.inc	(working copy)
>> @@ -20,6 +20,7 @@
>>
>>  obj-y += slot_1.o
>>  subdirs-y += ../model_6xx
>> +subdirs-y += ../model_6bx
>>  subdirs-y += ../../x86/tsc
>>  subdirs-y += ../../x86/mtrr
>>  subdirs-y += ../../x86/lapic
>> Index: src/cpu/intel/socket_PGA370/Makefile.inc
>> ===================================================================
>> --- src/cpu/intel/socket_PGA370/Makefile.inc	(revision 5527)
>> +++ src/cpu/intel/socket_PGA370/Makefile.inc	(working copy)
>> @@ -20,6 +20,7 @@
>>
>>  obj-y += socket_PGA370.o
>>  subdirs-y += ../model_6xx
>> +subdirs-y += ../model_6bx
>>  subdirs-y += ../../x86/tsc
>>  subdirs-y += ../../x86/mtrr
>>  subdirs-y += ../../x86/lapic
>>
>> ----- End patch -----
>>
> Hello Keith,
> I kind of saw this coming. That is why I left the 6bx's in model_6xx. The
> new model_6bx is intended for CAR, so I don't know how well it will work
> with romcc. My advice is to either get CAR running on your board, or we put
> back the 6bx's in model_6xx for the interim.
>
> --
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
>
Joseph Smith - 2010-05-07 17:28:41
On Fri, 7 May 2010 13:00:37 -0400, Keith Hui <buurin@gmail.com> wrote:
> I think I should get CAR running. But CAR is not quite developed for
> the rest of the 6xx family.
> 
Correct, and it will never get done if we don't step forward.

> If you look at the boot log you'll see that it got through to SeaBIOS
> just fine. My coreboot is still on romcc.
> 
> What are the steps needed to enable CAR on a board?
> 
Take a look at Thomson IP1000. Hope that helps.
Keith Hui - 2010-05-07 23:38:32
On Fri, May 7, 2010 at 7:01 PM, Idwer Vollering <vidwer@gmail.com> wrote:
>
>
> 2010/5/7 Keith Hui <buurin@gmail.com>
>>
>> I think I should get CAR running. But CAR is not quite developed for
>> the rest of the 6xx family.
>>
>> If you look at the boot log you'll see that it got through to SeaBIOS
>> just fine. My coreboot is still on romcc.
>>
>> What are the steps needed to enable CAR on a board?
>
> Example: see attached patch (as an example/reference only because
> USE_PRINTK_IN_CAR, in src/mainboard/asus/p2b/Kconfig, somehow breaks
> booting/serial output.. waiting for my pci post card to arrive).
>>

All that I can find with importance is two Kconfig options...

Booting failed with POST code 0x10.

Digging into code now.

Patch

Index: src/cpu/intel/slot_1/Makefile.inc
===================================================================
--- src/cpu/intel/slot_1/Makefile.inc	(revision 5527)
+++ src/cpu/intel/slot_1/Makefile.inc	(working copy)
@@ -20,6 +20,7 @@ 

 obj-y += slot_1.o
 subdirs-y += ../model_6xx
+subdirs-y += ../model_6bx
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
Index: src/cpu/intel/socket_PGA370/Makefile.inc
===================================================================
--- src/cpu/intel/socket_PGA370/Makefile.inc	(revision 5527)
+++ src/cpu/intel/socket_PGA370/Makefile.inc	(working copy)
@@ -20,6 +20,7 @@ 

 obj-y += socket_PGA370.o
 subdirs-y += ../model_6xx
+subdirs-y += ../model_6bx
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic