Patchwork inteltool patch: Added support to ICH9 chipset family

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Submitter Антон Кочков
Date 2010-05-07 11:27:58
Message ID <i2lc5dff2e81005070427o5e381c6djf7644927f382c24a@mail.gmail.com>
Download mbox | patch
Permalink /patch/1295/
State Superseded
Headers show

Comments

Антон Кочков - 2010-05-07 11:27:58
Added support to ICH9 chipset family
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
---

Patch

diff -c inteltool//gpio.c inteltool2//gpio.c
*** inteltool//gpio.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//gpio.c	2010-05-07 14:49:35.000000000 +0400
***************
*** 114,119 ****
--- 114,138 ----
  	{ 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
  };
  
+ static const io_register_t ich9_gpio_registers[] = {
+ 	{ 0x00, 4, "GPIO_USE_SEL" },
+ 	{ 0x04, 4, "GP_IO_SEL" },
+ 	{ 0x08, 4, "RESERVED" },
+ 	{ 0x0c, 4, "GP_LVL" },
+ 	{ 0x10, 4, "RESERVED" },
+ 	{ 0x14, 4, "RESERVED" },
+ 	{ 0x18, 4, "GPO_BLINK" },
+ 	{ 0x1c, 4, "GP_SER_BLINK" },
+ 	{ 0x20, 4, "GP_SB_CMDSTS" },
+ 	{ 0x24, 4, "GP_SB_DATA" },
+ 	{ 0x28, 4, "RESERVED" },
+ 	{ 0x2c, 4, "GPI_INV" },
+ 	{ 0x30, 4, "GPIO_USE_SEL2" },
+ 	{ 0x34, 4, "GP_IO_SEL2" },
+ 	{ 0x38, 4, "GP_LVL2" },
+ 	{ 0x3C, 4, "RESERVED" }
+ };
+ 
  
  int print_gpios(struct pci_dev *sb)
  {
***************
*** 124,129 ****
--- 143,158 ----
  	printf("\n============= GPIOS =============\n\n");
  
  	switch (sb->device_id) {
+         case PCI_DEVICE_ID_INTEL_ICH9DH:
+         case PCI_DEVICE_ID_INTEL_ICH9DO:
+         case PCI_DEVICE_ID_INTEL_ICH9R:
+         case PCI_DEVICE_ID_INTEL_ICH9:
+         case PCI_DEVICE_ID_INTEL_ICH9M:
+         case PCI_DEVICE_ID_INTEL_ICH9ME:
+                 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ 		gpio_registers = ich9_gpio_registers;
+ 		size = ARRAY_SIZE(ich9_gpio_registers);
+ 		break;
  	case PCI_DEVICE_ID_INTEL_ICH8M:
  		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
  		gpio_registers = ich8_gpio_registers;
diff -c inteltool//inteltool.c inteltool2//inteltool.c
*** inteltool//inteltool.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//inteltool.c	2010-05-07 14:39:17.000000000 +0400
***************
*** 45,52 ****
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
! 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
--- 45,59 ----
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
+         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45MEGMCH, "GS45ME-GMCH" }, // Northbridge in GS45
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
!         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
  	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
diff -c inteltool//inteltool.h inteltool2//inteltool.h
*** inteltool//inteltool.h	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//inteltool.h	2010-05-07 14:05:50.000000000 +0400
***************
*** 44,51 ****
--- 44,59 ----
  #define PCI_DEVICE_ID_INTEL_ICH7M		0x27b9
  #define PCI_DEVICE_ID_INTEL_ICH7MDH		0x27bd
  #define PCI_DEVICE_ID_INTEL_ICH8M		0x2815
+ #define PCI_DEVICE_ID_INTEL_ICH9DH              0x2912
+ #define PCI_DEVICE_ID_INTEL_ICH9DO              0x2914
+ #define PCI_DEVICE_ID_INTEL_ICH9R               0x2916
+ #define PCI_DEVICE_ID_INTEL_ICH9                0x2918
+ #define PCI_DEVICE_ID_INTEL_ICH9M               0x2919
+ #define PCI_DEVICE_ID_INTEL_ICH9ME              0x2917
  #define PCI_DEVICE_ID_INTEL_ICH10R		0x3a16
  
+ #define PCI_DEVICE_ID_INTEL_GS45MEGMCH          0x2a40 // northbridge  GS45
+ 
  #define PCI_DEVICE_ID_INTEL_82810		0x7120
  #define PCI_DEVICE_ID_INTEL_82810DC		0x7122
  #define PCI_DEVICE_ID_INTEL_82830M		0x3575
diff -c inteltool//memory.c inteltool2//memory.c
*** inteltool//memory.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//memory.c	2010-05-07 14:25:25.000000000 +0400
***************
*** 54,59 ****
--- 54,63 ----
  	case PCI_DEVICE_ID_INTEL_82830M:
  		printf("This northbrigde does not have MCHBAR.\n");
  		return 1;
+         case PCI_DEVICE_ID_INTEL_GS45MEGMCH:
+                 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
+                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+  		break;
  	default:
  		printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
  		return 1;
diff -c inteltool//pcie.c inteltool2//pcie.c
*** inteltool//pcie.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//pcie.c	2010-05-07 14:40:40.000000000 +0400
***************
*** 43,48 ****
--- 43,49 ----
   	case PCI_DEVICE_ID_INTEL_82Q35:
   	case PCI_DEVICE_ID_INTEL_82G33:
   	case PCI_DEVICE_ID_INTEL_82Q33:
+         case PCI_DEVICE_ID_INTEL_GS45MEGMCH:
   		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
   		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
   		break;
***************
*** 51,57 ****
  	case PCI_DEVICE_ID_INTEL_82830M:
  		printf("This northbrigde does not have EPBAR.\n");
  		return 1;
! 	default:
  		printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
  		return 1;
  	}
--- 52,58 ----
  	case PCI_DEVICE_ID_INTEL_82830M:
  		printf("This northbrigde does not have EPBAR.\n");
  		return 1;
!         default:
  		printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
  		return 1;
  	}
***************
*** 95,109 ****
   	case PCI_DEVICE_ID_INTEL_82Q35:
   	case PCI_DEVICE_ID_INTEL_82G33:
   	case PCI_DEVICE_ID_INTEL_82Q33:
   		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
   		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
   		break;
  	case PCI_DEVICE_ID_INTEL_82810:
  	case PCI_DEVICE_ID_INTEL_82810DC:
- 	case PCI_DEVICE_ID_INTEL_82830M:
  		printf("This northbrigde does not have DMIBAR.\n");
  		return 1;
! 	default:
  		printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
  		return 1;
  	}
--- 96,110 ----
   	case PCI_DEVICE_ID_INTEL_82Q35:
   	case PCI_DEVICE_ID_INTEL_82G33:
   	case PCI_DEVICE_ID_INTEL_82Q33:
+         case PCI_DEVICE_ID_INTEL_GS45MEGMCH:
   		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
   		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
   		break;
  	case PCI_DEVICE_ID_INTEL_82810:
  	case PCI_DEVICE_ID_INTEL_82810DC:
  		printf("This northbrigde does not have DMIBAR.\n");
  		return 1;
!         default:
  		printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
  		return 1;
  	}
***************
*** 149,154 ****
--- 150,156 ----
   	case PCI_DEVICE_ID_INTEL_82Q35:
   	case PCI_DEVICE_ID_INTEL_82G33:
   	case PCI_DEVICE_ID_INTEL_82Q33:
+         case PCI_DEVICE_ID_INTEL_GS45MEGMCH:
   		pciexbar_reg = pci_read_long(nb, 0x60);
   		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
   		break;
diff -c inteltool//powermgt.c inteltool2//powermgt.c
*** inteltool//powermgt.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//powermgt.c	2010-05-07 15:12:12.000000000 +0400
***************
*** 21,67 ****
  #include <stdio.h>
  #include "inteltool.h"
  
! static const io_register_t ich7_pm_registers[] = {
! 	{ 0x00, 2, "PM1_STS" },
! 	{ 0x02, 2, "PM1_EN" },
! 	{ 0x04, 4, "PM1_CNT" },
! 	{ 0x08, 4, "PM1_TMR" },
  	{ 0x0c, 4, "RESERVED" },
! 	{ 0x10, 4, "PROC_CNT" },
  #if DANGEROUS_REGISTERS
  	/* These registers return 0 on read, but reading them may cause
! 	 * the system to enter C2/C3/C4 state, which might hang the system.
  	 */
! 	{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
! 	{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
! 	{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
  #endif
! 	{ 0x17, 1, "RESERVED" },
! 	{ 0x18, 4, "RESERVED" },
  	{ 0x1c, 4, "RESERVED" },
! 	{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
! 	{ 0x21, 1, "RESERVED" },
! 	{ 0x22, 2, "RESERVED" },
! 	{ 0x24, 4, "RESERVED" },
! 	{ 0x28, 4, "GPE0_STS" },
! 	{ 0x2C, 4, "GPE0_EN" },
  	{ 0x30, 4, "SMI_EN" },
  	{ 0x34, 4, "SMI_STS" },
  	{ 0x38, 2, "ALT_GP_SMI_EN" },
  	{ 0x3a, 2, "ALT_GP_SMI_STS" },
! 	{ 0x3c, 4, "RESERVED" },
! 	{ 0x40, 2, "RESERVED" },
  	{ 0x42, 1, "GPE_CNTL" },
  	{ 0x43, 1, "RESERVED" },
! 	{ 0x44, 2, "DEVACT_STS" },
  	{ 0x46, 2, "RESERVED" },
  	{ 0x48, 4, "RESERVED" },
  	{ 0x4c, 4, "RESERVED" },
! 	{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
  	{ 0x51, 1, "RESERVED" },
  	{ 0x52, 2, "RESERVED" },
! 	{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
! 	{ 0x58, 4, "RESERVED" },
  	{ 0x5c, 4, "RESERVED" },
  	/* Here start the TCO registers */
  	{ 0x60, 2, "TCO_RLD" },
--- 21,67 ----
  #include <stdio.h>
  #include "inteltool.h"
  
! static const io_register_t ich9_pm_registers[] = {
! 	{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
! 	{ 0x02, 2, "PM1_EN" },  // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
! 	{ 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
! 	{ 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
  	{ 0x0c, 4, "RESERVED" },
! 	{ 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
  #if DANGEROUS_REGISTERS
  	/* These registers return 0 on read, but reading them may cause
! 	 * the system to enter Cx states, which might hang the system.
  	 */
! 	{ 0x14, 1, "LV2 (Mobile)" },
! 	{ 0x15, 1, "LV3 (Mobile)" },
! 	{ 0x16, 1, "LV4 (Mobile)" },
! 	{ 0x17, 1, "LV5 (Mobile)" },
! 	{ 0x18, 1, "LV6 (Mobile)" },
  #endif
! 	{ 0x19, 1, "RESERVED" },
! 	{ 0x1a, 2, "RESERVED" },
  	{ 0x1c, 4, "RESERVED" },
! 	{ 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
! 	{ 0x2C, 4, "GPE0_EN" },  // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
  	{ 0x30, 4, "SMI_EN" },
  	{ 0x34, 4, "SMI_STS" },
  	{ 0x38, 2, "ALT_GP_SMI_EN" },
  	{ 0x3a, 2, "ALT_GP_SMI_STS" },
! 	{ 0x3c, 1, "UPRWC" },   // USB Per-Port registers write control;
!         { 0x3d, 2, "RESERVED" },
!         { 0x3f, 1, "RESERVED" },
!         { 0x40, 2, "RESERVED" },
  	{ 0x42, 1, "GPE_CNTL" },
  	{ 0x43, 1, "RESERVED" },
! 	{ 0x44, 2, "DEVACT_STS" }, // Device Activity Status
  	{ 0x46, 2, "RESERVED" },
  	{ 0x48, 4, "RESERVED" },
  	{ 0x4c, 4, "RESERVED" },
! 	{ 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
  	{ 0x51, 1, "RESERVED" },
  	{ 0x52, 2, "RESERVED" },
! 	{ 0x54, 4, "C3_RES (Mobile)" },
! 	{ 0x58, 4, "C5_RES (Mobile)" },
  	{ 0x5c, 4, "RESERVED" },
  	/* Here start the TCO registers */
  	{ 0x60, 2, "TCO_RLD" },
***************
*** 145,150 ****
--- 145,211 ----
  	{ 0x7c, 4, "RESERVED" },
  };
  
+ static const io_register_t ich7_pm_registers[] = {
+ 	{ 0x00, 2, "PM1_STS" },
+ 	{ 0x02, 2, "PM1_EN" },
+ 	{ 0x04, 4, "PM1_CNT" },
+ 	{ 0x08, 4, "PM1_TMR" },
+ 	{ 0x0c, 4, "RESERVED" },
+ 	{ 0x10, 4, "PROC_CNT" },
+ #if DANGEROUS_REGISTERS
+ 	/* These registers return 0 on read, but reading them may cause
+ 	 * the system to enter C2/C3/C4 state, which might hang the system.
+ 	 */
+ 	{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
+ 	{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
+ 	{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
+ #endif
+ 	{ 0x17, 1, "RESERVED" },
+ 	{ 0x18, 4, "RESERVED" },
+ 	{ 0x1c, 4, "RESERVED" },
+ 	{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
+ 	{ 0x21, 1, "RESERVED" },
+ 	{ 0x22, 2, "RESERVED" },
+ 	{ 0x24, 4, "RESERVED" },
+ 	{ 0x28, 4, "GPE0_STS" },
+ 	{ 0x2C, 4, "GPE0_EN" },
+ 	{ 0x30, 4, "SMI_EN" },
+ 	{ 0x34, 4, "SMI_STS" },
+ 	{ 0x38, 2, "ALT_GP_SMI_EN" },
+ 	{ 0x3a, 2, "ALT_GP_SMI_STS" },
+ 	{ 0x3c, 4, "RESERVED" },
+ 	{ 0x40, 2, "RESERVED" },
+ 	{ 0x42, 1, "GPE_CNTL" },
+ 	{ 0x43, 1, "RESERVED" },
+ 	{ 0x44, 2, "DEVACT_STS" },
+ 	{ 0x46, 2, "RESERVED" },
+ 	{ 0x48, 4, "RESERVED" },
+ 	{ 0x4c, 4, "RESERVED" },
+ 	{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+ 	{ 0x51, 1, "RESERVED" },
+ 	{ 0x52, 2, "RESERVED" },
+ 	{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
+ 	{ 0x58, 4, "RESERVED" },
+ 	{ 0x5c, 4, "RESERVED" },
+ 	/* Here start the TCO registers */
+ 	{ 0x60, 2, "TCO_RLD" },
+ 	{ 0x62, 1, "TCO_DAT_IN" },
+ 	{ 0x63, 1, "TCO_DAT_OUT" },
+ 	{ 0x64, 2, "TCO1_STS" },
+ 	{ 0x66, 2, "TCO2_STS" },
+ 	{ 0x68, 2, "TCO1_CNT" },
+ 	{ 0x6a, 2, "TCO2_CNT" },
+ 	{ 0x6c, 2, "TCO_MESSAGE" },
+ 	{ 0x6e, 1, "TCO_WDCNT" },
+ 	{ 0x6f, 1, "RESERVED" },
+ 	{ 0x70, 1, "SW_IRQ_GEN" },
+ 	{ 0x71, 1, "RESERVED" },
+ 	{ 0x72, 2, "TCO_TMR" },
+ 	{ 0x74, 4, "RESERVED" },
+ 	{ 0x78, 4, "RESERVED" },
+ 	{ 0x7c, 4, "RESERVED" },
+ };
+ 
  /*
   * INTEL I/O Controller Hub 6 Family
   * http://www.intel.com/assets/pdf/datasheet/301473.pdf
***************
*** 357,362 ****
--- 418,433 ----
  		pm_registers = ich7_pm_registers;
  		size = ARRAY_SIZE(ich7_pm_registers);
  		break;
+         case PCI_DEVICE_ID_INTEL_ICH9DH:
+         case PCI_DEVICE_ID_INTEL_ICH9DO:
+         case PCI_DEVICE_ID_INTEL_ICH9R:
+         case PCI_DEVICE_ID_INTEL_ICH9:
+         case PCI_DEVICE_ID_INTEL_ICH9M:
+         case PCI_DEVICE_ID_INTEL_ICH9ME:
+ 		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ 		pm_registers = ich9_pm_registers;
+ 		size = ARRAY_SIZE(ich9_pm_registers);
+ 		break;
  	case PCI_DEVICE_ID_INTEL_ICH8M:
  		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
  		pm_registers = ich8_pm_registers;
diff -c inteltool//rootcmplx.c inteltool2//rootcmplx.c
*** inteltool//rootcmplx.c	2010-05-07 15:16:54.878775130 +0400
--- inteltool2//rootcmplx.c	2010-05-07 14:27:39.000000000 +0400
***************
*** 36,41 ****
--- 36,47 ----
  	case PCI_DEVICE_ID_INTEL_ICH7M:
  	case PCI_DEVICE_ID_INTEL_ICH7DH:
  	case PCI_DEVICE_ID_INTEL_ICH7MDH:
+         case PCI_DEVICE_ID_INTEL_ICH9DH:
+         case PCI_DEVICE_ID_INTEL_ICH9DO:
+         case PCI_DEVICE_ID_INTEL_ICH9R:
+         case PCI_DEVICE_ID_INTEL_ICH9:
+         case PCI_DEVICE_ID_INTEL_ICH9M:
+         case PCI_DEVICE_ID_INTEL_ICH9ME:
  	case PCI_DEVICE_ID_INTEL_ICH8M:
  		rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
  		break;
Only in inteltool/: .svn