Patchwork Include headers instead of sources in romstage, part 1/many

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Submitter Patrick Georgi
Date 2010-05-07 22:13:19
Message ID <4BE4907F.5030202@georgi-clan.de>
Download mbox | patch
Permalink /patch/1297/
State Accepted
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Comments

Patrick Georgi - 2010-05-07 22:13:19
Hi,

attached patch drops console/console.c and pc80/serial.c from the
mainboards' romstage.c. console/console.h is included instead.

On CAR builds, console/console.c is built separately and linked to the
romstage, on romcc builds, this includes console/console.c from within
console/console.h.
The romcc variant helps with uniformity.

In the same way, pc80/serial.c is eliminated from romstage.c. The
necessary prototypes were already included via some other paths.

Both files needs to include arch/io.h for separate compilation, so it
finds outb, so it's moved outside the #ifndef __PRE_RAM__ in console.c
and added in serial.c

The patch also removes two superfluous ARRAY_SIZE definitions (in
amd/db800 and winent/pl6064)

It's abuild tested and

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Stefan Reinauer - 2010-05-08 08:25:57
On 5/8/10 12:13 AM, Patrick Georgi wrote:
> -#initobj-y += serial.o
> +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
>  subdirs-y += vga
>  
>   
Awesome... the less .c file includes we have in romstage.c the better..

This way works in the case of converting code that was previously always
compiled in.

But how should we handle things in case of other conditions?

Acked-by: Stefan Reinauer <stepan@coresystems.de>

Stefan
Patrick Georgi - 2010-05-08 08:34:23
Am Samstag, den 08.05.2010, 10:25 +0200 schrieb Stefan Reinauer:
> On 5/8/10 12:13 AM, Patrick Georgi wrote:
> > -#initobj-y += serial.o
> > +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
> >  subdirs-y += vga
> >  
> >   
> Awesome... the less .c file includes we have in romstage.c the better..
> 
> This way works in the case of converting code that was previously always
> compiled in.
> 
> But how should we handle things in case of other conditions?
We could stuff all of the initobjs into an initobj.a, and use that for
linking. ld will only pick up the object files that are actually needed
then. This means we probably compile a serial port thingy too many, but
they're rather small.

For chipset specific stuff (once we get there), it can be
initobj-$(CONFIG_SOUTHBRIDGE_X_Y) += ...


Patrick
Kevin O'Connor - 2010-05-08 15:56:46
On Sat, May 08, 2010 at 10:34:23AM +0200, Patrick Georgi wrote:
> Am Samstag, den 08.05.2010, 10:25 +0200 schrieb Stefan Reinauer:
> > On 5/8/10 12:13 AM, Patrick Georgi wrote:
> > > -#initobj-y += serial.o
> > > +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
> > >  subdirs-y += vga
> > Awesome... the less .c file includes we have in romstage.c the better..
> > 
> > This way works in the case of converting code that was previously always
> > compiled in.
> > 
> > But how should we handle things in case of other conditions?
> We could stuff all of the initobjs into an initobj.a, and use that for
> linking. ld will only pick up the object files that are actually needed
> then. This means we probably compile a serial port thingy too many, but
> they're rather small.

I think coreboot should try to avoid using .a files.

The latest version of gcc (v4.5) contains the -flto feature.  This can
provide significant benefits to coreboot code generation because it
allows the entire romstage (and ramstage) to be analyzed as a whole.
The resulting binaries are significantly smaller because unused code
can be eliminated and more functions can be inlined.  Unfortunately,
the standard linker can't handle -flto with .a files.

-Kevin
Patrick Georgi - 2010-05-08 15:59:19
Am 08.05.2010 17:56, schrieb Kevin O'Connor:
> I think coreboot should try to avoid using .a files.
> 
> The latest version of gcc (v4.5) contains the -flto feature.  This can
> provide significant benefits to coreboot code generation because it
> allows the entire romstage (and ramstage) to be analyzed as a whole.
> The resulting binaries are significantly smaller because unused code
> can be eliminated and more functions can be inlined.  Unfortunately,
> the standard linker can't handle -flto with .a files.
Our build system is advanced enough that this can be an option based on
compiler version.

Thanks for the notice, but I guess we should support non-lto builds
until gcc4.5 is the lowest common denominator, or even better the next
version, so we can assume that bugs are fixed.


Patrick
Stefan Reinauer - 2010-05-08 16:22:54
On 5/8/10 5:56 PM, Kevin O'Connor wrote:
> I think coreboot should try to avoid using .a files.
>
> The latest version of gcc (v4.5) contains the -flto feature.  This can
> provide significant benefits to coreboot code generation because it
> allows the entire romstage (and ramstage) to be analyzed as a whole.
> The resulting binaries are significantly smaller because unused code
> can be eliminated and more functions can be inlined.  Unfortunately,
> the standard linker can't handle -flto with .a files.
>   
The reason we used .a files to begin with was because the linker can
smartly drop unused objects files "linked" into a static library,
significantly decreasing code size.

Going to -flto introduces one code size reduction mechanism by rendering
another one unusable. That's only half-baked, especially since many
optimizations making -flto useful are still known broken in gcc 4.5. We
should keep this in mind. Last time I checked -flto on a coreboot image
it would not gain more than 1-2kb on a 1MB image. Didn't benchmark the
4.5 release yet though.

Being curious: Will gold cope with .a files and flto?
Kevin O'Connor - 2010-05-08 16:40:27
On Sat, May 08, 2010 at 06:22:54PM +0200, Stefan Reinauer wrote:
> On 5/8/10 5:56 PM, Kevin O'Connor wrote:
> > I think coreboot should try to avoid using .a files.
> >
> > The latest version of gcc (v4.5) contains the -flto feature.  This can
> > provide significant benefits to coreboot code generation because it
> > allows the entire romstage (and ramstage) to be analyzed as a whole.
> > The resulting binaries are significantly smaller because unused code
> > can be eliminated and more functions can be inlined.  Unfortunately,
> > the standard linker can't handle -flto with .a files.
> >   
> The reason we used .a files to begin with was because the linker can
> smartly drop unused objects files "linked" into a static library,
> significantly decreasing code size.

Yeah, but I've not had much luck with that optimization because it's
too easy to inadvertently pull in .o files.  I've had more success
with enabling -ffunction-sections / -fdata-sections and giving ld the
--gc-sections option.

> Going to -flto introduces one code size reduction mechanism by rendering
> another one unusable. That's only half-baked, especially since many
> optimizations making -flto useful are still known broken in gcc 4.5. We
> should keep this in mind. Last time I checked -flto on a coreboot image
> it would not gain more than 1-2kb on a 1MB image. Didn't benchmark the
> 4.5 release yet though.

I use -fwhole-program in seabios and find it quite useful.  I haven't
done much with -flto, but it is supposed to allow -fwhole-program
without having to completely restructure the build process.  It's more
than just a size optimization, though I suspect that's the biggest
impact coreboot would see.

> Being curious: Will gold cope with .a files and flto?

Yes (according to the gcc documentation).

See the -flto description at:

http://gcc.gnu.org/onlinedocs/gcc-4.5.0/gcc/Optimize-Options.html#Optimize-Options

-Kevin

Patch

Index: src/include/console/console.h
===================================================================
--- src/include/console/console.h	(revision 5527)
+++ src/include/console/console.h	(working copy)
@@ -307,4 +307,9 @@ 
 
 #endif
 
+#ifdef __ROMCC__
+/* if included by romcc, include the sources, too. romcc can't use prototypes */
+#include <console/console.c>
+#endif
+
 #endif /* CONSOLE_CONSOLE_H_ */
Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c	(revision 5527)
+++ src/mainboard/iwill/dk8_htx/romstage.c	(working copy)
@@ -29,8 +29,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c	(revision 5527)
+++ src/mainboard/iwill/dk8s2/romstage.c	(working copy)
@@ -29,8 +29,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c	(revision 5527)
+++ src/mainboard/iwill/dk8x/romstage.c	(working copy)
@@ -29,8 +29,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/axus/tc320/romstage.c
===================================================================
--- src/mainboard/axus/tc320/romstage.c	(revision 5527)
+++ src/mainboard/axus/tc320/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/bcom/winnetp680/romstage.c
===================================================================
--- src/mainboard/bcom/winnetp680/romstage.c	(revision 5527)
+++ src/mainboard/bcom/winnetp680/romstage.c	(working copy)
@@ -26,8 +26,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/bcom/winnet100/romstage.c
===================================================================
--- src/mainboard/bcom/winnet100/romstage.c	(revision 5527)
+++ src/mainboard/bcom/winnet100/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/televideo/tc7020/romstage.c
===================================================================
--- src/mainboard/televideo/tc7020/romstage.c	(revision 5527)
+++ src/mainboard/televideo/tc7020/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/asrock/939a785gmh/romstage.c
===================================================================
--- src/mainboard/asrock/939a785gmh/romstage.c	(revision 5527)
+++ src/mainboard/asrock/939a785gmh/romstage.c	(working copy)
@@ -43,8 +43,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/broadcom/blast/romstage.c
===================================================================
--- src/mainboard/broadcom/blast/romstage.c	(revision 5527)
+++ src/mainboard/broadcom/blast/romstage.c	(working copy)
@@ -13,8 +13,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/thomson/ip1000/romstage.c
===================================================================
--- src/mainboard/thomson/ip1000/romstage.c	(revision 5527)
+++ src/mainboard/thomson/ip1000/romstage.c	(working copy)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <arch/llshell.h>
-#include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
Index: src/mainboard/supermicro/x6dai_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/x6dai_g/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
Index: src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/h8dmr/romstage.c	(working copy)
@@ -49,8 +49,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/supermicro/x6dhe_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/x6dhe_g/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/h8dme/romstage.c	(working copy)
@@ -46,8 +46,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c	(working copy)
@@ -44,8 +44,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c	(working copy)
@@ -44,8 +44,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/supermicro/x6dhe_g2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/x6dhe_g2/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
Index: src/mainboard/supermicro/x6dhr_ig/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/x6dhr_ig/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
Index: src/mainboard/supermicro/x6dhr_ig2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/romstage.c	(revision 5527)
+++ src/mainboard/supermicro/x6dhr_ig2/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(revision 5527)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/kontron/986lcd-m/romstage.c
===================================================================
--- src/mainboard/kontron/986lcd-m/romstage.c	(revision 5527)
+++ src/mainboard/kontron/986lcd-m/romstage.c	(working copy)
@@ -46,8 +46,6 @@ 
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/kontron/kt690/romstage.c
===================================================================
--- src/mainboard/kontron/kt690/romstage.c	(revision 5527)
+++ src/mainboard/kontron/kt690/romstage.c	(working copy)
@@ -43,8 +43,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/a-trend/atc-6240/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6240/romstage.c	(revision 5527)
+++ src/mainboard/a-trend/atc-6240/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/a-trend/atc-6220/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6220/romstage.c	(revision 5527)
+++ src/mainboard/a-trend/atc-6220/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/romstage.c	(revision 5527)
+++ src/mainboard/gigabyte/m57sli/romstage.c	(working copy)
@@ -51,8 +51,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(revision 5527)
+++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(working copy)
@@ -53,8 +53,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/gigabyte/ga-6bxc/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/romstage.c	(revision 5527)
+++ src/mainboard/gigabyte/ga-6bxc/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/digitallogic/msm800sev/romstage.c
===================================================================
--- src/mainboard/digitallogic/msm800sev/romstage.c	(revision 5527)
+++ src/mainboard/digitallogic/msm800sev/romstage.c	(working copy)
@@ -4,8 +4,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/digitallogic/adl855pc/romstage.c
===================================================================
--- src/mainboard/digitallogic/adl855pc/romstage.c	(revision 5527)
+++ src/mainboard/digitallogic/adl855pc/romstage.c	(working copy)
@@ -8,8 +8,7 @@ 
 #include <stdlib.h>
 #include "pc80/udelay_io.c"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
Index: src/mainboard/digitallogic/msm586seg/romstage.c
===================================================================
--- src/mainboard/digitallogic/msm586seg/romstage.c	(revision 5527)
+++ src/mainboard/digitallogic/msm586seg/romstage.c	(working copy)
@@ -6,7 +6,7 @@ 
 #include <arch/hlt.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 //#include "lib/delay.c"
Index: src/mainboard/mitac/6513wu/romstage.c
===================================================================
--- src/mainboard/mitac/6513wu/romstage.c	(revision 5527)
+++ src/mainboard/mitac/6513wu/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/olpc/btest/romstage.c
===================================================================
--- src/mainboard/olpc/btest/romstage.c	(revision 5527)
+++ src/mainboard/olpc/btest/romstage.c	(working copy)
@@ -5,7 +5,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/olpc/rev_a/romstage.c
===================================================================
--- src/mainboard/olpc/rev_a/romstage.c	(revision 5527)
+++ src/mainboard/olpc/rev_a/romstage.c	(working copy)
@@ -5,7 +5,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/emulation/qemu-x86/romstage.c
===================================================================
--- src/mainboard/emulation/qemu-x86/romstage.c	(revision 5527)
+++ src/mainboard/emulation/qemu-x86/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
Index: src/mainboard/technologic/ts5300/romstage.c
===================================================================
--- src/mainboard/technologic/ts5300/romstage.c	(revision 5527)
+++ src/mainboard/technologic/ts5300/romstage.c	(working copy)
@@ -12,7 +12,7 @@ 
 #include <arch/hlt.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 
Index: src/mainboard/nokia/ip530/romstage.c
===================================================================
--- src/mainboard/nokia/ip530/romstage.c	(revision 5527)
+++ src/mainboard/nokia/ip530/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/amd/mahogany/romstage.c
===================================================================
--- src/mainboard/amd/mahogany/romstage.c	(revision 5527)
+++ src/mainboard/amd/mahogany/romstage.c	(working copy)
@@ -42,8 +42,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/amd/pistachio/romstage.c
===================================================================
--- src/mainboard/amd/pistachio/romstage.c	(revision 5527)
+++ src/mainboard/amd/pistachio/romstage.c	(working copy)
@@ -36,8 +36,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/amd/dbm690t/romstage.c
===================================================================
--- src/mainboard/amd/dbm690t/romstage.c	(revision 5527)
+++ src/mainboard/amd/dbm690t/romstage.c	(working copy)
@@ -42,8 +42,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/amd/rumba/romstage.c
===================================================================
--- src/mainboard/amd/rumba/romstage.c	(revision 5527)
+++ src/mainboard/amd/rumba/romstage.c	(working copy)
@@ -5,7 +5,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c	(revision 5527)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c	(working copy)
@@ -29,8 +29,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include <reset.h>
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c	(revision 5527)
+++ src/mainboard/amd/mahogany_fam10/romstage.c	(working copy)
@@ -47,8 +47,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
Index: src/mainboard/amd/tilapia_fam10/romstage.c
===================================================================
--- src/mainboard/amd/tilapia_fam10/romstage.c	(revision 5527)
+++ src/mainboard/amd/tilapia_fam10/romstage.c	(working copy)
@@ -47,8 +47,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
Index: src/mainboard/amd/norwich/romstage.c
===================================================================
--- src/mainboard/amd/norwich/romstage.c	(revision 5527)
+++ src/mainboard/amd/norwich/romstage.c	(working copy)
@@ -23,8 +23,7 @@ 
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(revision 5527)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(working copy)
@@ -47,8 +47,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
Index: src/mainboard/amd/db800/romstage.c
===================================================================
--- src/mainboard/amd/db800/romstage.c	(revision 5527)
+++ src/mainboard/amd/db800/romstage.c	(working copy)
@@ -19,13 +19,12 @@ 
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
 #include <console/console.h>
-#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
@@ -33,7 +32,6 @@ 
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
Index: src/mainboard/biostar/m6tba/romstage.c
===================================================================
--- src/mainboard/biostar/m6tba/romstage.c	(revision 5527)
+++ src/mainboard/biostar/m6tba/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/rca/rm4100/romstage.c
===================================================================
--- src/mainboard/rca/rm4100/romstage.c	(revision 5527)
+++ src/mainboard/rca/rm4100/romstage.c	(working copy)
@@ -25,9 +25,8 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
Index: src/mainboard/azza/pt-6ibd/romstage.c
===================================================================
--- src/mainboard/azza/pt-6ibd/romstage.c	(revision 5527)
+++ src/mainboard/azza/pt-6ibd/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/nec/powermate2000/romstage.c
===================================================================
--- src/mainboard/nec/powermate2000/romstage.c	(revision 5527)
+++ src/mainboard/nec/powermate2000/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/iei/nova4899r/romstage.c
===================================================================
--- src/mainboard/iei/nova4899r/romstage.c	(revision 5527)
+++ src/mainboard/iei/nova4899r/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
Index: src/mainboard/iei/pcisa-lx-800-r10/romstage.c
===================================================================
--- src/mainboard/iei/pcisa-lx-800-r10/romstage.c	(revision 5527)
+++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c	(working copy)
@@ -23,8 +23,7 @@ 
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/iei/juki-511p/romstage.c
===================================================================
--- src/mainboard/iei/juki-511p/romstage.c	(revision 5527)
+++ src/mainboard/iei/juki-511p/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
Index: src/mainboard/hp/dl145_g3/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g3/romstage.c	(revision 5527)
+++ src/mainboard/hp/dl145_g3/romstage.c	(working copy)
@@ -57,8 +57,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/hp/e_vectra_p2706t/romstage.c
===================================================================
--- src/mainboard/hp/e_vectra_p2706t/romstage.c	(revision 5527)
+++ src/mainboard/hp/e_vectra_p2706t/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 /* TODO: It's a PC87364 actually! */
 #include "superio/nsc/pc87360/pc87360_early_serial.c"
Index: src/mainboard/tyan/s2912/romstage.c
===================================================================
--- src/mainboard/tyan/s2912/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2912/romstage.c	(working copy)
@@ -51,8 +51,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/tyan/s2850/romstage.c
===================================================================
--- src/mainboard/tyan/s2850/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2850/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2735/romstage.c
===================================================================
--- src/mainboard/tyan/s2735/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2735/romstage.c	(working copy)
@@ -8,8 +8,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
Index: src/mainboard/tyan/s2880/romstage.c
===================================================================
--- src/mainboard/tyan/s2880/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2880/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s1846/romstage.c
===================================================================
--- src/mainboard/tyan/s1846/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s1846/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/tyan/s2881/romstage.c
===================================================================
--- src/mainboard/tyan/s2881/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2881/romstage.c	(working copy)
@@ -13,8 +13,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2882/romstage.c
===================================================================
--- src/mainboard/tyan/s2882/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2882/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2891/romstage.c
===================================================================
--- src/mainboard/tyan/s2891/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2891/romstage.c	(working copy)
@@ -14,8 +14,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s4880/romstage.c
===================================================================
--- src/mainboard/tyan/s4880/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s4880/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2892/romstage.c
===================================================================
--- src/mainboard/tyan/s2892/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2892/romstage.c	(working copy)
@@ -14,8 +14,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2875/romstage.c
===================================================================
--- src/mainboard/tyan/s2875/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2875/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s4882/romstage.c
===================================================================
--- src/mainboard/tyan/s4882/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s4882/romstage.c	(working copy)
@@ -8,8 +8,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2885/romstage.c
===================================================================
--- src/mainboard/tyan/s2885/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2885/romstage.c	(working copy)
@@ -8,8 +8,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2895/romstage.c
===================================================================
--- src/mainboard/tyan/s2895/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2895/romstage.c	(working copy)
@@ -15,8 +15,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c	(revision 5527)
+++ src/mainboard/tyan/s2912_fam10/romstage.c	(working copy)
@@ -45,8 +45,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/pcengines/alix1c/romstage.c
===================================================================
--- src/mainboard/pcengines/alix1c/romstage.c	(revision 5527)
+++ src/mainboard/pcengines/alix1c/romstage.c	(working copy)
@@ -24,8 +24,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/artecgroup/dbe61/romstage.c
===================================================================
--- src/mainboard/artecgroup/dbe61/romstage.c	(revision 5527)
+++ src/mainboard/artecgroup/dbe61/romstage.c	(working copy)
@@ -25,8 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/asi/mb_5blgp/romstage.c
===================================================================
--- src/mainboard/asi/mb_5blgp/romstage.c	(revision 5527)
+++ src/mainboard/asi/mb_5blgp/romstage.c	(working copy)
@@ -24,7 +24,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/asi/mb_5blmp/romstage.c
===================================================================
--- src/mainboard/asi/mb_5blmp/romstage.c	(revision 5527)
+++ src/mainboard/asi/mb_5blmp/romstage.c	(working copy)
@@ -25,7 +25,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
Index: src/mainboard/lippert/roadrunner-lx/romstage.c
===================================================================
--- src/mainboard/lippert/roadrunner-lx/romstage.c	(revision 5527)
+++ src/mainboard/lippert/roadrunner-lx/romstage.c	(working copy)
@@ -27,8 +27,7 @@ 
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/lippert/frontrunner/romstage.c
===================================================================
--- src/mainboard/lippert/frontrunner/romstage.c	(revision 5527)
+++ src/mainboard/lippert/frontrunner/romstage.c	(working copy)
@@ -5,7 +5,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/lippert/spacerunner-lx/romstage.c
===================================================================
--- src/mainboard/lippert/spacerunner-lx/romstage.c	(revision 5527)
+++ src/mainboard/lippert/spacerunner-lx/romstage.c	(working copy)
@@ -28,8 +28,7 @@ 
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/abit/be6-ii_v2_0/romstage.c
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/romstage.c	(revision 5527)
+++ src/mainboard/abit/be6-ii_v2_0/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/via/epia-m700/romstage.c
===================================================================
--- src/mainboard/via/epia-m700/romstage.c	(revision 5527)
+++ src/mainboard/via/epia-m700/romstage.c	(working copy)
@@ -33,8 +33,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/vx800/vx800.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/vt8454c/romstage.c
===================================================================
--- src/mainboard/via/vt8454c/romstage.c	(revision 5527)
+++ src/mainboard/via/vt8454c/romstage.c	(working copy)
@@ -26,8 +26,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cx700/raminit.h"
 #include "cpu/x86/bist.h"
Index: src/mainboard/via/epia-m/romstage.c
===================================================================
--- src/mainboard/via/epia-m/romstage.c	(revision 5527)
+++ src/mainboard/via/epia-m/romstage.c	(working copy)
@@ -7,7 +7,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/vt8623/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia-n/romstage.c
===================================================================
--- src/mainboard/via/epia-n/romstage.c	(revision 5527)
+++ src/mainboard/via/epia-n/romstage.c	(working copy)
@@ -27,7 +27,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia-cn/romstage.c
===================================================================
--- src/mainboard/via/epia-cn/romstage.c	(revision 5527)
+++ src/mainboard/via/epia-cn/romstage.c	(working copy)
@@ -26,8 +26,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia/romstage.c
===================================================================
--- src/mainboard/via/epia/romstage.c	(revision 5527)
+++ src/mainboard/via/epia/romstage.c	(working copy)
@@ -6,7 +6,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/vt8601/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/pc2500e/romstage.c
===================================================================
--- src/mainboard/via/pc2500e/romstage.c	(revision 5527)
+++ src/mainboard/via/pc2500e/romstage.c	(working copy)
@@ -27,8 +27,7 @@ 
 #include <arch/hlt.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/dell/s1850/romstage.c
===================================================================
--- src/mainboard/dell/s1850/romstage.c	(revision 5527)
+++ src/mainboard/dell/s1850/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
Index: src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(revision 5527)
+++ src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/roda/rk886ex/romstage.c
===================================================================
--- src/mainboard/roda/rk886ex/romstage.c	(revision 5527)
+++ src/mainboard/roda/rk886ex/romstage.c	(working copy)
@@ -39,8 +39,6 @@ 
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/msi/ms7135/romstage.c
===================================================================
--- src/mainboard/msi/ms7135/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms7135/romstage.c	(working copy)
@@ -50,8 +50,7 @@ 
 #define CK804_USE_ACI 1
 
 #include <cpu/amd/model_fxx_rev.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
Index: src/mainboard/msi/ms6119/romstage.c
===================================================================
--- src/mainboard/msi/ms6119/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms6119/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms6147/romstage.c
===================================================================
--- src/mainboard/msi/ms6147/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms6147/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms6156/romstage.c
===================================================================
--- src/mainboard/msi/ms6156/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms6156/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms9282/romstage.c	(working copy)
@@ -44,8 +44,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
Index: src/mainboard/msi/ms6178/romstage.c
===================================================================
--- src/mainboard/msi/ms6178/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms6178/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/msi/ms9185/romstage.c
===================================================================
--- src/mainboard/msi/ms9185/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms9185/romstage.c	(working copy)
@@ -49,8 +49,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms9652_fam10/romstage.c	(working copy)
@@ -45,8 +45,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c	(revision 5527)
+++ src/mainboard/msi/ms7260/romstage.c	(working copy)
@@ -55,8 +55,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/arima/hdama/romstage.c
===================================================================
--- src/mainboard/arima/hdama/romstage.c	(revision 5527)
+++ src/mainboard/arima/hdama/romstage.c	(working copy)
@@ -7,8 +7,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/sunw/ultra40/romstage.c
===================================================================
--- src/mainboard/sunw/ultra40/romstage.c	(revision 5527)
+++ src/mainboard/sunw/ultra40/romstage.c	(working copy)
@@ -16,8 +16,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/advantech/pcm-5820/romstage.c
===================================================================
--- src/mainboard/advantech/pcm-5820/romstage.c	(revision 5527)
+++ src/mainboard/advantech/pcm-5820/romstage.c	(working copy)
@@ -24,7 +24,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/eaglelion/5bcm/romstage.c
===================================================================
--- src/mainboard/eaglelion/5bcm/romstage.c	(revision 5527)
+++ src/mainboard/eaglelion/5bcm/romstage.c	(working copy)
@@ -6,7 +6,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/newisys/khepri/romstage.c
===================================================================
--- src/mainboard/newisys/khepri/romstage.c	(revision 5527)
+++ src/mainboard/newisys/khepri/romstage.c	(working copy)
@@ -14,8 +14,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/jetway/j7f24/romstage.c
===================================================================
--- src/mainboard/jetway/j7f24/romstage.c	(revision 5527)
+++ src/mainboard/jetway/j7f24/romstage.c	(working copy)
@@ -26,8 +26,7 @@ 
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/technexion/tim8690/romstage.c
===================================================================
--- src/mainboard/technexion/tim8690/romstage.c	(revision 5527)
+++ src/mainboard/technexion/tim8690/romstage.c	(working copy)
@@ -42,8 +42,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/technexion/tim5690/romstage.c
===================================================================
--- src/mainboard/technexion/tim5690/romstage.c	(revision 5527)
+++ src/mainboard/technexion/tim5690/romstage.c	(working copy)
@@ -42,8 +42,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/winent/pl6064/romstage.c
===================================================================
--- src/mainboard/winent/pl6064/romstage.c	(revision 5527)
+++ src/mainboard/winent/pl6064/romstage.c	(working copy)
@@ -20,12 +20,12 @@ 
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
@@ -33,7 +33,6 @@ 
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
Index: src/mainboard/ibm/e326/romstage.c
===================================================================
--- src/mainboard/ibm/e326/romstage.c	(revision 5527)
+++ src/mainboard/ibm/e326/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/ibm/e325/romstage.c
===================================================================
--- src/mainboard/ibm/e325/romstage.c	(revision 5527)
+++ src/mainboard/ibm/e325/romstage.c	(working copy)
@@ -9,8 +9,7 @@ 
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/romstage.c	(revision 5527)
+++ src/mainboard/nvidia/l1_2pvv/romstage.c	(working copy)
@@ -51,8 +51,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/intel/xe7501devkit/romstage.c
===================================================================
--- src/mainboard/intel/xe7501devkit/romstage.c	(revision 5527)
+++ src/mainboard/intel/xe7501devkit/romstage.c	(working copy)
@@ -9,7 +9,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
Index: src/mainboard/intel/d945gclf/romstage.c
===================================================================
--- src/mainboard/intel/d945gclf/romstage.c	(revision 5527)
+++ src/mainboard/intel/d945gclf/romstage.c	(working copy)
@@ -37,8 +37,6 @@ 
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/intel/truxton/romstage.c
===================================================================
--- src/mainboard/intel/truxton/romstage.c	(revision 5527)
+++ src/mainboard/intel/truxton/romstage.c	(working copy)
@@ -29,7 +29,7 @@ 
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
Index: src/mainboard/intel/mtarvon/romstage.c
===================================================================
--- src/mainboard/intel/mtarvon/romstage.c	(revision 5527)
+++ src/mainboard/intel/mtarvon/romstage.c	(working copy)
@@ -28,7 +28,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
Index: src/mainboard/intel/eagleheights/romstage.c
===================================================================
--- src/mainboard/intel/eagleheights/romstage.c	(revision 5527)
+++ src/mainboard/intel/eagleheights/romstage.c	(working copy)
@@ -32,8 +32,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/x86/bist.h>
 
 #include "lib/ramtest.c"
Index: src/mainboard/intel/jarrell/romstage.c
===================================================================
--- src/mainboard/intel/jarrell/romstage.c	(revision 5527)
+++ src/mainboard/intel/jarrell/romstage.c	(working copy)
@@ -8,7 +8,7 @@ 
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(revision 5527)
+++ src/mainboard/asus/p2b-ls/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/mew-am/romstage.c
===================================================================
--- src/mainboard/asus/mew-am/romstage.c	(revision 5527)
+++ src/mainboard/asus/mew-am/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/asus/p2b/romstage.c
===================================================================
--- src/mainboard/asus/p2b/romstage.c	(revision 5527)
+++ src/mainboard/asus/p2b/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p2b-d/romstage.c
===================================================================
--- src/mainboard/asus/p2b-d/romstage.c	(revision 5527)
+++ src/mainboard/asus/p2b-d/romstage.c	(working copy)
@@ -27,7 +27,7 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p2b-f/romstage.c
===================================================================
--- src/mainboard/asus/p2b-f/romstage.c	(revision 5527)
+++ src/mainboard/asus/p2b-f/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c	(revision 5527)
+++ src/mainboard/asus/a8v-e_se/romstage.c	(working copy)
@@ -46,8 +46,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/asus/p2b-ds/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ds/romstage.c	(revision 5527)
+++ src/mainboard/asus/p2b-ds/romstage.c	(working copy)
@@ -27,7 +27,7 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p3b-f/romstage.c
===================================================================
--- src/mainboard/asus/p3b-f/romstage.c	(revision 5527)
+++ src/mainboard/asus/p3b-f/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/mew-vm/romstage.c
===================================================================
--- src/mainboard/asus/mew-vm/romstage.c	(revision 5527)
+++ src/mainboard/asus/mew-vm/romstage.c	(working copy)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/asus/a8n_e/romstage.c
===================================================================
--- src/mainboard/asus/a8n_e/romstage.c	(revision 5527)
+++ src/mainboard/asus/a8n_e/romstage.c	(working copy)
@@ -48,8 +48,7 @@ 
 #define CK804_NUM 1
 
 #include <cpu/amd/model_fxx_rev.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
Index: src/mainboard/asus/m2v-mx_se/romstage.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/romstage.c	(revision 5527)
+++ src/mainboard/asus/m2v-mx_se/romstage.c	(working copy)
@@ -51,8 +51,7 @@ 
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/console/console.c
===================================================================
--- src/console/console.c	(revision 5527)
+++ src/console/console.c	(working copy)
@@ -5,9 +5,9 @@ 
 #include <console/console.h>
 #include <build.h>
 #include <arch/hlt.h>
+#include <arch/io.h>
 
 #ifndef __PRE_RAM__
-#include <arch/io.h>
 #include <string.h>
 #include <pc80/mc146818rtc.h>
 
Index: src/console/Makefile.inc
===================================================================
--- src/console/Makefile.inc	(revision 5527)
+++ src/console/Makefile.inc	(working copy)
@@ -7,6 +7,7 @@ 
 smmobj-y += vtxprintf.o
 
 initobj-y += vtxprintf.o
+initobj-$(CONFIG_USE_DCACHE_RAM) += console.o
 
 driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o
 driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o
Index: src/pc80/serial.c
===================================================================
--- src/pc80/serial.c	(revision 5527)
+++ src/pc80/serial.c	(working copy)
@@ -1,4 +1,5 @@ 
 #include <lib.h> /* Prototypes */
+#include <arch/io.h>
 
 /* Base Address */
 #ifndef CONFIG_TTYS0_BASE
Index: src/pc80/Makefile.inc
===================================================================
--- src/pc80/Makefile.inc	(revision 5527)
+++ src/pc80/Makefile.inc	(working copy)
@@ -4,7 +4,7 @@ 
 obj-$(CONFIG_UDELAY_IO) += udelay_io.o
 obj-y += keyboard.o
 
-#initobj-y += serial.o
+initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
 subdirs-y += vga
 
 $(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H)