Patchwork Move includes to files that actually use them

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Submitter Patrick Georgi
Date 2010-05-09 20:47:15
Message ID <4BE71F53.8030104@georgi-clan.de>
Download mbox | patch
Permalink /patch/1312/
State Accepted
Commit r5539
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Comments

Patrick Georgi - 2010-05-09 20:47:15
Hi,

as part of the ongoing quest to clean up the code to make it easier to
use and adapt, I added a couple of #include statements to AMD code, so
it gains some self-sufficiency.

These includes are necessary because those files use their definitions.
It only works so far because the romstage carefully includes files in
the right order so everything is included before it's needed by another
file.

This change, and similar ones that will come after it, allow us to
simplify the romstage.c of boards that use these chipsets (ie. Fam10 for
this patch), making it easier to support new boards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Stefan Reinauer - 2010-05-09 21:04:44
On 5/9/10 10:47 PM, Patrick Georgi wrote:
> Hi,
>
> as part of the ongoing quest to clean up the code to make it easier to
> use and adapt, I added a couple of #include statements to AMD code, so
> it gains some self-sufficiency.
>
> These includes are necessary because those files use their definitions.
> It only works so far because the romstage carefully includes files in
> the right order so everything is included before it's needed by another
> file.
>
> This change, and similar ones that will come after it, allow us to
> simplify the romstage.c of boards that use these chipsets (ie. Fam10 for
> this patch), making it easier to support new boards.
>
> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
>   
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Patch

Index: src/include/cpu/amd/model_10xxx_msr.h
===================================================================
--- src/include/cpu/amd/model_10xxx_msr.h	(revision 5530)
+++ src/include/cpu/amd/model_10xxx_msr.h	(working copy)
@@ -20,6 +20,8 @@ 
 #ifndef CPU_AMD_MODEL_10XXX_MSR_H
 #define CPU_AMD_MODEL_10XXX_MSR_H
 
+#include <cpu/x86/msr.h>
+
 #define HWCR_MSR			0xC0010015
 #define NB_CFG_MSR			0xC001001f
 #define LS_CFG_MSR			0xC0011020
Index: src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
===================================================================
--- src/superio/smsc/smscsuperio/smscsuperio_early_serial.c	(revision 5530)
+++ src/superio/smsc/smscsuperio/smscsuperio_early_serial.c	(working copy)
@@ -19,6 +19,7 @@ 
  */
 
 #include <arch/romcc_io.h>
+#include <device/pnp_def.h>
 
 /* All known/supported SMSC Super I/Os have the same logical device IDs
  * for the serial ports (COM1, COM2).
Index: src/cpu/amd/quadcore/quadcore.c
===================================================================
--- src/cpu/amd/quadcore/quadcore.c	(revision 5530)
+++ src/cpu/amd/quadcore/quadcore.c	(working copy)
@@ -17,6 +17,7 @@ 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 
 #ifndef SET_NB_CFG_54
 	#define SET_NB_CFG_54 1
Index: src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- src/cpu/amd/car/post_cache_as_ram.c	(revision 5530)
+++ src/cpu/amd/car/post_cache_as_ram.c	(working copy)
@@ -1,6 +1,7 @@ 
 /* 2005.6 by yhlu
  * 2006.3 yhlu add copy data from CAR to ram
  */
+#include <string.h>
 #include <arch/stages.h>
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
Index: src/cpu/amd/model_10xxx/defaults.h
===================================================================
--- src/cpu/amd/model_10xxx/defaults.h	(revision 5530)
+++ src/cpu/amd/model_10xxx/defaults.h	(working copy)
@@ -17,6 +17,8 @@ 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <cpu/amd/mtrr.h>
 
 /*
  * Default MSR and errata settings.
Index: src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_10xxx/init_cpus.c	(revision 5530)
+++ src/cpu/amd/model_10xxx/init_cpus.c	(working copy)
@@ -18,6 +18,12 @@ 
  */
 
 #include "defaults.h"
+#include <stdlib.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/porting.h>
 
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID
Index: src/northbridge/amd/amdmct/mct/mctmtr_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct/mctmtr_d.c	(revision 5530)
+++ src/northbridge/amd/amdmct/mct/mctmtr_d.c	(working copy)
@@ -19,6 +19,7 @@ 
 
 
 #include "mct_d.h"
+#include <cpu/amd/mtrr.h>
 
 static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);
 static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);
Index: src/northbridge/amd/amdht/ht_wrapper.c
===================================================================
--- src/northbridge/amd/amdht/ht_wrapper.c	(revision 5530)
+++ src/northbridge/amd/amdht/ht_wrapper.c	(working copy)
@@ -17,6 +17,9 @@ 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 
 /*----------------------------------------------------------------------------
  *			TYPEDEFS, DEFINITIONS AND MACROS
Index: src/arch/i386/include/stddef.h
===================================================================
--- src/arch/i386/include/stddef.h	(revision 5530)
+++ src/arch/i386/include/stddef.h	(working copy)
@@ -8,7 +8,9 @@ 
 typedef int wchar_t;
 typedef unsigned int wint_t;
 
+#ifndef NULL
 #define NULL ((void *)0)
+#endif
 
 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)