===================================================================
@@ -145,7 +145,7 @@ static void clear_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
- * [ 6: 6] Reserved
+ * [ 6: 6] Destination SubLink (must be 0 if not ganged)
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
@@ -154,14 +154,14 @@ static void clear_resource_map(void)
* address that defines the end of a memory-mapped
* I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00000000,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -219,15 +219,16 @@ static void clear_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
- * [11: 6] Reserved
+ * [ 6: 6] Destination SubLink (must be 0 if not ganged)
+ * [11: 7] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -291,7 +292,8 @@ static void clear_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
- * [15:10] Reserved
+ * [10:10] Destination SubLink (must be 0 if not ganged)
+ * [15:11] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in
* configuration region i
@@ -299,10 +301,10 @@ static void clear_resource_map(void)
* This field defines the highest bus number in
* configuration regin i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
u32 max;
===================================================================
@@ -120,7 +120,7 @@ static void setup_mb_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
- * [ 6: 6] Reserved
+ * [ 6: 6] Destination SubLink (must be 0 if not ganged)
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
@@ -128,14 +128,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -192,15 +192,16 @@ static void setup_mb_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
- * [11: 6] Reserved
+ * [ 6: 6] Destination SubLink (must be 0 if not ganged)
+ * [11: 7] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -262,16 +263,17 @@ static void setup_mb_resource_map(void)
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
- * [15:10] Reserved
+ * [10:10] Destination SubLink (must be 0 if not ganged)
+ * [15:11] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x06000003, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
int max;
===================================================================
@@ -128,14 +128,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -197,10 +197,10 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -268,10 +268,10 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x06000003, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
int max;
===================================================================
@@ -128,14 +128,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -197,10 +197,10 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -268,10 +268,10 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x06000003, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
int max;
===================================================================
@@ -129,14 +129,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -198,11 +198,11 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00004000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x00004000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -273,10 +273,10 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
/* Verified against board configuration registers after normal proprietary BIOS boot */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
===================================================================
@@ -129,14 +129,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -199,10 +199,10 @@ static void setup_mb_resource_map(void)
* [31:25] Reserved
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff020,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -272,10 +272,10 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
===================================================================
@@ -129,14 +129,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000008, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000008, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -199,10 +199,10 @@ static void setup_mb_resource_map(void)
* [31:25] Reserved
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000F88, 0x01fff020,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000F88, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000F88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000F88, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -272,10 +272,10 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000F888, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000F888, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000F888, 0x00000000,
};
===================================================================
@@ -26,7 +26,7 @@ static void setup_mb_resource_map(void)
* contain the enables */
/* Memory-Mapped I/O Limit i Registers */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000008, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
I think there's too much duplication in the resource map code. resourcemaps.diff tries to address it by: Creating clear_resource_map() for k8 and fam10. This sets all the routing registers to a known state. Calling clear_resource_map() and then only setting the specific registers that are non-zero in board-specific code. Adding util.c for fam10, so that it can be customized for fam10. I didn't update all of the resourcemap.c files, yet. I wanted to see what the reaction would be. sublinks.diff marks that bit as not reserved for all fam10 boards, so that it can be cleared. Signed-off-by: Myles Watson <mylesgw@gmail.com> Thanks, Myles