Patchwork watchdog mcp55's codec initialization loops

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Submitter Joe Korty
Date 2010-05-12 15:12:45
Message ID <20100512151245.GA14873@tsunami.ccur.com>
Download mbox | patch
Permalink /patch/1319/
State New
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Comments

Joe Korty - 2010-05-12 15:12:45
Put a 1 msec watchdog on the mcp55's codec status-wait
loops.

This 'fixes' a coreboot lockup I saw on my SuperMicro
H8DME-2 with AMD 2222 Processors installed.

For some reason the codec is being found but the
subsequent initialization sequence is not able to
initialize the device.

Hopefully a 1 msec watchdog is long enough for a found
codec.  If not it can be made longer but hopefully it
can be kept much shorter than 1 second as excessively
long timeouts make it difficult to use coreboot as a
'quick boot' mechanism.
Myles Watson - 2010-05-12 15:54:23
> Put a 1 msec watchdog on the mcp55's codec status-wait
> loops.
> For some reason the codec is being found but the
> subsequent initialization sequence is not able to
> initialize the device.

I wonder if the address is somehow wrong, or not routed correctly.

> +	if (!i) {
> +		printk(BIOS_WARNING, "2: codec(%08x,%d) timed out.  Not set
> up.\n", base, addr);
> +		return;
> +	}

What's the output when it fails?

Thanks,
Myles
Joe Korty - 2010-05-12 15:59:10
On Wed, May 12, 2010 at 11:54:23AM -0400, Myles Watson wrote:
> 
> 
> > Put a 1 msec watchdog on the mcp55's codec status-wait
> > loops.
> > For some reason the codec is being found but the
> > subsequent initialization sequence is not able to
> > initialize the device.
> 
> I wonder if the address is somehow wrong, or not routed correctly.
> 
> > +	if (!i) {
> > +		printk(BIOS_WARNING, "2: codec(%08x,%d) timed out.  Not set
> > up.\n", base, addr);
> > +		return;
> > +	}
> 
> What's the output when it fails?


It's .....

	PCI: 00:06.1 init
	base = 0xfc140000
	codec_mask = 01
	2: codec(fc140000,0) timed out.  Not set up.
	PCI: 00:08.0 init

Regards,
Joe
Myles Watson - 2010-05-12 16:19:52
> -----Original Message-----
> From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org]
> On Behalf Of Joe Korty
> Sent: Wednesday, May 12, 2010 9:59 AM
> To: Myles Watson
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] [PATCH] watchdog mcp55's codec initialization
> loops
> 
> On Wed, May 12, 2010 at 11:54:23AM -0400, Myles Watson wrote:
> >
> >
> > > Put a 1 msec watchdog on the mcp55's codec status-wait
> > > loops.
> > > For some reason the codec is being found but the
> > > subsequent initialization sequence is not able to
> > > initialize the device.
> >
> > I wonder if the address is somehow wrong, or not routed correctly.
> >
> > > +	if (!i) {
> > > +		printk(BIOS_WARNING, "2: codec(%08x,%d) timed out.  Not set
> > > up.\n", base, addr);
> > > +		return;
> > > +	}
> >
> > What's the output when it fails?
> 
> 
> It's .....
> 
> 	PCI: 00:06.1 init
> 	base = 0xfc140000
> 	codec_mask = 01
> 	2: codec(fc140000,0) timed out.  Not set up.
> 	PCI: 00:08.0 init

I'd try to figure out if the read is failing.  If you print out dword (the
read value), is it 0xffffffff (probably not responding to the read)?
Earlier in the boot log does it look like fc14 is the correct address for
one of the resources for PCI 6.1?  Does it get enabled before this in the
log?

Thanks,
Myles
Joe Korty - 2010-05-12 20:23:39
On Wed, May 12, 2010 at 12:19:52PM -0400, Myles Watson wrote:
> I'd try to figure out if the read is failing.  If you print out dword (the
> read value), is it 0xffffffff (probably not responding to the read)?
> Earlier in the boot log does it look like fc14 is the correct address for
> one of the resources for PCI 6.1?  Does it get enabled before this in the
> log?

The dword at point the '2: codec(f9f40000,0) timed out' message is 0.
The mapped device address (different this time as my PCI card mix has
changed) appears to be consistant with the built-in audio device.  Raw data:

lspci -v:

	00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2)
		Subsystem: Super Micro Computer Inc Unknown device 1511
		Flags: 66MHz, fast devsel, IRQ 23
		Memory at f9f40000 (32-bit, non-prefetchable) [size=16K]
		Capabilities: [44] Power Management version 2
		Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable
	-
		Capabilities: [6c] HyperTransport: MSI Mapping


coreboot ttyS0 log:
	PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
	PCI: 00:18.0 allocate_resources_mem: base:f8000000 size:2000000 align:23 gran:20 limit:febfffff
	Assigned: PCI: 00:0e.0 20 *  [0xf8000000 - 0xf9dfffff] mem
	Assigned: PCI: 00:06.0 20 *  [0xf9e00000 - 0xf9efffff] mem
	Assigned: PCI: 00:01.3 10 *  [0xf9f00000 - 0xf9f3ffff] mem
	Assigned: PCI: 00:06.1 10 *  [0xf9f40000 - 0xf9f43fff] mem
	Assigned: PCI: 00:01.0 14 *  [0xf9f44000 - 0xf9f44fff] mem
	Assigned: PCI: 00:02.0 10 *  [0xf9f45000 - 0xf9f45fff] mem
	Assigned: PCI: 00:05.0 24 *  [0xf9f46000 - 0xf9f46fff] mem
	Assigned: PCI: 00:05.1 24 *  [0xf9f47000 - 0xf9f47fff] mem
...

	PCI: 00:06.0 assign_resources, bus 1 link: 0
	PCI: 00:06.1 10 <- [0x00f9f40000 - 0x00f9f43fff] size 0x00004000 gran 0x0e mem
	PCI: 00:08.0 10 <- [0x00f9f49000 - 0x00f9f49fff] size 0x00001000 gran 0x0c mem
	PCI: 00:08.0 14 <- [0x000000b030 - 0x000000b037] size 0x00000008 gran 0x03 io
	PCI: 00:08.0 18 <- [0x00f9f4b100 - 0x00f9f4b1ff] size 0x00000100 gran 0x08 mem
...
	PCI: 01:05.0 resource base f9e00000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
	PCI: 01:06.0 links 0 child on link 0 NULL
	PCI: 00:06.1 links 0 child on link 0 NULL
	PCI: 00:06.1 resource base f9f40000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10
	PCI: 00:08.0 links 0 child on link 0 NULL
	PCI: 00:08.0 resource base f9f49000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
	PCI: 00:08.0 resource base b030 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
...
	SATA S  SATA P 
	PCI: 00:05.2 init
	SATA S  SATA P 
	PCI: 00:06.0 init
	PCI DOMAIN mem base = 0x00e8000000
	[0x50] <-- 0xe8000000
	PCI: 00:06.1 init
	base = 0xf9f40000
	codec_mask = 01
	2: codec(f9f40000,0) timed out.  Not set up.
	dword = 00000000
	PCI: 00:08.0 init
	MCP55 MAC PHY ID 0x01410c00 PHY ADDR 2
	Check CBFS header at fffeffe0
	magic is 4f524243
	Found CBFS header at fffeffe0
	Check fallback/coreboot_ram
Myles Watson - 2010-05-12 20:38:47
> On Wed, May 12, 2010 at 12:19:52PM -0400, Myles Watson wrote:
> > I'd try to figure out if the read is failing.  If you print out dword
> (the
> > read value), is it 0xffffffff (probably not responding to the read)?
> > Earlier in the boot log does it look like fc14 is the correct address
> for
> > one of the resources for PCI 6.1?  Does it get enabled before this in
> the
> > log?
> 
> The dword at point the '2: codec(f9f40000,0) timed out' message is 0.
> The mapped device address (different this time as my PCI card mix has
> changed) appears to be consistant with the built-in audio device.  Raw
> data:
Unfortunately, I don't see an obvious problem.  Everything looks good until
the failure.

Good luck,
Myles

Patch

Index: trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c
===================================================================
--- trunk.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c	2010-05-12 06:33:16.000000000 -0400
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c	2010-05-12 07:05:51.000000000 -0400
@@ -173,16 +173,28 @@ 
 	int i;
 
 	/* 1 */
+	i = 100; /* 1 msec watchdog */
 	do {
+		udelay(10);
 		dword = read32(base + 0x68);
-	} while (dword & 1);
+	} while ((dword & 1) && --i);
+	if (!i) {
+		printk(BIOS_WARNING, "1: codec(%08x,%d) timed out.  Not set up.\n", base, addr);
+		return;
+	}
 
 	dword = (addr<<28) | 0x000f0000;
 	write32(base + 0x60, dword);
 
+	i = 100; /* 1 msec watchdog */
 	do {
+		udelay(10);
 		dword = read32(base + 0x68);
-	} while ((dword & 3)!=2);
+	} while (((dword & 3) != 2) && --i);
+	if (!i) {
+		printk(BIOS_WARNING, "2: codec(%08x,%d) timed out.  Not set up.\n", base, addr);
+		return;
+	}
 
 	dword = read32(base + 0x64);