Patchwork watchdog mcp55's codec initialization loops

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Submitter Stefan Reinauer
Date 2010-05-13 14:42:40
Message ID <4BEC0FE0.8080409@coresystems.de>
Download mbox | patch
Permalink /patch/1322/
State Accepted
Headers show

Comments

Stefan Reinauer - 2010-05-13 14:42:40
On 5/12/10 5:12 PM, Joe Korty wrote:
> Put a 1 msec watchdog on the mcp55's codec status-wait
> loops.
>
> This 'fixes' a coreboot lockup I saw on my SuperMicro
> H8DME-2 with AMD 2222 Processors installed.
>
> For some reason the codec is being found but the
> subsequent initialization sequence is not able to
> initialize the device.
>
> Hopefully a 1 msec watchdog is long enough for a found
> codec.  If not it can be made longer but hopefully it
> can be kept much shorter than 1 second as excessively
> long timeouts make it difficult to use coreboot as a
> 'quick boot' mechanism.
Hi Joe,

the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a
while ago and now I ported my version of the Azalia code to MCP55 /
H8DME (assuming that's the board target you use for the H8DME-2)
Can you please see if this is any better than before? It's likely that
the verb table won't match the codec used on that board, but there only
was a single codec in the mcp55 driver and the used codec is usually
mainboard dependent, not chipset dependent.

Stefan
Joe Korty - 2010-05-13 15:08:22
On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote:
> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a
> while ago and now I ported my version of the Azalia code to MCP55 /
> H8DME (assuming that's the board target you use for the H8DME-2)
> Can you please see if this is any better than before? It's likely that
> the verb table won't match the codec used on that board, but there only
> was a single codec in the mcp55 driver and the used codec is usually
> mainboard dependent, not chipset dependent.


It works!!!
But I didn't hear a beep during coreboot.  Was I supposed to?

Regards, and thanks,
Joe
Stefan Reinauer - 2010-05-13 15:40:36
On 5/13/10 5:08 PM, Joe Korty wrote:
> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote:
>   
>> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a
>> while ago and now I ported my version of the Azalia code to MCP55 /
>> H8DME (assuming that's the board target you use for the H8DME-2)
>> Can you please see if this is any better than before? It's likely that
>> the verb table won't match the codec used on that board, but there only
>> was a single codec in the mcp55 driver and the used codec is usually
>> mainboard dependent, not chipset dependent.
>>     
>
> It works!!!
> But I didn't hear a beep during coreboot.  Was I supposed to?
>   
No, no beeps... The driver just initializes the codec.

If someone had a nice piece of code to output a sample on azalia
devices, I think we should make it an option. I looked at alsa some time
ago but found it less than trivial to extract the info useful for us.

Could you please send a log file containing the output of the new azalia
driver?

Stefan
Joe Korty - 2010-05-13 16:56:27
On Thu, May 13, 2010 at 11:40:36AM -0400, Stefan Reinauer wrote:
>On 5/13/10 5:08 PM, Joe Korty wrote:
>> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote:
>>   
>>> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a
>>> while ago and now I ported my version of the Azalia code to MCP55 /
>>> H8DME (assuming that's the board target you use for the H8DME-2)
>>> Can you please see if this is any better than before? It's likely that
>>> the verb table won't match the codec used on that board, but there only
>>> was a single codec in the mcp55 driver and the used codec is usually
>>> mainboard dependent, not chipset dependent.
>>     
>> It works!!!
>> But I didn't hear a beep during coreboot.  Was I supposed to?
>
> No, no beeps... The driver just initializes the codec.
>
> If someone had a nice piece of code to output a sample on azalia
> devices, I think we should make it an option. I looked at alsa some time
> ago but found it less than trivial to extract the info useful for us.
>
> Could you please send a log file containing the output of the new azalia
> driver?

Sure.  Here it is....
Regards,
Joe
--------------------------------------------------------------------

INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---

Issuing SOFT_RESET...


coreboot-4.0-r5543M Thu May 13 08:55:53 EDT 2010 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started:  01
started ap apicid: * AP 01started
* AP 03started

SBLink=02
NC node|link=02
begin msr fid, vid 31081208080c020c
end   msr fid, vid 31081208080c020c
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0xca, unfiltered freq_cap=0x8075
pos=0xca, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
mcp55_num:01
SMBus controller enabled
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram1.01
setting up CPU 01 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000cee34
Enabling dual channel memory
Registered
333MHz
333MHz
RAM end at 0x00200000 kB
Ram2.01
sdram_set_spd_registers: paramx :000cee34
Enabling dual channel memory
Registered
333MHz
333MHz
RAM end at 0x00400000 kB
Ram3
ECC enabled
ECC enabled
Initializing memory:  done
Initializing memory:  done
RAM end at 0x00500000 kB
set DQS timing:RcvrEn:Pass1: 00
 done
set DQS timing:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce9a0
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
TrainDQSPos: MutualCSPassW[48] :000ce874
 done
set DQS timing:RcvrEn:Pass2: 00
 done
Total DQS Training : tsc [00]=0000001bc57f58f7
Total DQS Training : tsc [01]=0000001bc6b671be
Total DQS Training : tsc [02]=0000001c0b0d9cce
Total DQS Training : tsc [03]=0000001c0c187dce
Ram4
v_esp=000ceea8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
 oading stage CiOmDaEg eI.N
eROChMe cAkN DC BRFUSN  hOeNa dNeOrD Ea:t  fffe0f1f
 0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
mtaTgrea:i nlDoQaSdRidnWgr Pfoasl:l bbaucfk_/ac:or0e0b0ocoet9_br0a
  @ T0rxa1i0n0D0Q0S0P o(s4:0 9M6u0t0u ablyCtSePsa)s,s We[n4t8r]y  :@0 000xc1e0800040

TrainDQSPos: MutualCSPassW[48] :000ce884
TrainDQSPos: MutualCSPassW[48] :000ce884
utage: Tdroanien DlQoSaPdoisn:g .M
0tJuuamlpCiSnPga stsoW [i4m8a]g e:.0
o0ccoer8e8b4o
 t-4.0-r5543M Thu May 13 08:55:53 EDT 2010 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
:NP: T0r0a2ien.D1Q:S Peonsa:b lMeudt u0a,l C2S PraesssoWu[r4c8e]s 
e0P0N0Pc:e 808042
 .2: enabled 1, 2 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.5: enabled 1, 4 resources
PNP: 002e.6: enabled 0, 1 resources
PNP: 002e.7: enabled 0, 3 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 2 resources
PCI: 00:01.1: enabled 1, 0 resources
I2C: 00:48: enabled 0, 0 resources
l2C: 00:49: enablTerda i0n,D Q0S Proess:o uMructeusa
,CIS2PCa:s s0W0[:4581]:  :e0n0a0bclee8d8 41
  0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:02.1: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:05.1: enabled 1, 0 resources
PCI: 00:05.2: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:06.1: enabled 1, 0 resources
PCI: 00:08.0: enabled 1, 0 resources
aCI: 00:09.0: enableTdr a1i,n D0Q SrPeosso:u rMcuetsu
1lPCCSIP:a s0s0W:[04a8.]0 :: 0e0n0acbel8e8d4 
 , 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:04.1: enabled 1, 0 resources
PCI: 00:0b.0: enabled 1, 0 resources
PCI: 00:0c.0: enabled 1, 0 resources
PCI: 00:0d.0: enabled 1, 0 resources
PCI: 00:0e.0: enabled 1, 0 resources
PCI: 00:0f.0: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
lCI: 00:18.2: enablTerda i1n,D Q0S Proess:o uMructeusa
 CPSCPIa:s s0W0[:4188]. 3::0 0e0ncaeb8l8e4d
 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 0, 2 resources
]   PNP: 00T2rea.i2n:D QeSnPaobsl:e dM u1t,u a2l CrSePsaosusrWc[e4s8
0  : 0 0 0PcNeP8:8 40
 2e.3: enabled 0, 2 resources
    PNP: 002e.5: enabled 1, 4 resources
    PNP: 002e.6: enabled 0, 1 resources
    PNP: 002e.7: enabled 0, 3 resources
    PNP: 002e.8: enabled 0, 0 resources
    PNP: 002e.9: enabled 0, 0 resources
    PNP: 002e.a: enabled 0, 0 resources
    PNP: 002e.b: enabled 1, 2 resources
   PCI: 00:01.1: enabled 1, 0 resources
    I2C: 00:48: enabled 0, 0 resources
    I2C: 00:49: enabled 0, 0 resources
    I2C: 00:51: enabled 1, 0 resources
T r a iPnCDIQ:S P0o0s::0 2M.u0t:u aelnCaSbPlaesds W1[,4 80]  r:e0s0o0ucrec8e8s4

   PCI: 00:02.1: enabled 1, 0 resources
   PCI: 00:04.0: enabled 1, 0 resources
   PCI: 00:05.0: enabled 1, 0 resources
   PCI: 00:05.1: enabled 1, 0 resources
   PCI: 00:05.2: enabled 1, 0 resources
   PCI: 00:06.0: enabled 1, 0 resources
    PCI: 00:06.0: enabled 1, 0 resources
   PCI: 00:06.1: enabled 1, 0 resources
   PCI: 00:08.0: enabled 1, 0 resources
   PCI: 00:09.0: enabled 1, 0 resources
   PCI: 00:0a.0: enabled 1, 0 resources
u   PCI: 00:00.0: enabled 1T,r a0i nrDeQsSoPuorsc:e sM
 t u a l CPSCPIa:s s0W0[:4080]. 1::0 0e0ncaeb8l8e4d
 1, 0 resources
     PCI: 00:04.0: enabled 1, 0 resources
     PCI: 00:04.1: enabled 1, 0 resources
   PCI: 00:0b.0: enabled 1, 0 resources
   PCI: 00:0c.0: enabled 1, 0 resources
   PCI: 00:0d.0: enabled 1, 0 resources
   PCI: 00:0e.0: enabled 1, 0 resources
   PCI: 00:0f.0: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
Scan_static_Tbruasi nfDoQrS PRooso:t  MDuetvuiacleC
bPAaPsIsCW_[C4L8U]S T:E0R0:0 c0e 8e8n4a
 led
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
malloc Enter, size 1092, free_mem_ptr 00160000
malloc 00160000
CPU: APIC: 01 enabled
malloc Enter, size 1092, free_mem_ptr 00160444
malloc 00160444
PCI: 00:19.0 [1022/1100] bus ops
PCI: 00:19.0 [1022/1100] enabled
malloc Enter, size 1092, free_mem_ptr 00160888
malloc 00160888
PCI: 00:19.1 [1022/1101] enabled
malloc TErnatienrD,Q SsPiozse:  1M0u9t2u,a lfCrSePea_smseWm[_4p8t]r  :0000106c0ec8c8c4

malloc 00160ccc
PCI: 00:19.2 [1022/1102] enabled
malloc Enter, size 1092, free_mem_ptr 00161110
malloc 00161110
PCI: 00:19.3 [1022/1103] ops
PCI: 00:19.3 [1022/1103] enabled
  PCI: 00:19.3 siblings=1
malloc Enter, size 1092, free_mem_ptr 00161554
malloc 00161554
CPU: APIC: 02 enabled
malloc Enter, size 1092, free_mem_ptr 00161998
malloc 00161998
CPU: APIC: 03 enabled
PCI_DOMAIN: 0000 scanning...
sCI: pTcria_isncDaQnS_Pbouss:  fMourt ubaulsC S0P0a
2sPWC[I4:8 ]0 0::01080.c0e 8[8140
 2/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] enabled
PCI: Using configuration type 1
PCI: 00:00.0 [10de/0369] ops
 CI: 00:00.0 [10de/03T6r9a]i neDnQaSbPloesd:
4MCuatpuaabliClSiPtays:s Wt[y4p8e]  0:x00080 c@e 808x44

flags: 0x01e0
PCI: 00:00.0 count: 000f static_count: 0010
PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [10de/0369] enabled
PCI: 00:01.0 [10de/0364] bus ops
PCI: 00:01.0 [10de/0364] enabled
PCI: 00:01.1 [10de/0368] bus ops
PCI: 00:01.1 [10de/0368] enabled
malloc Enter, size 1092, free_mem_ptr 00161ddc
malloc 00161ddc
PCI: 00:01.2 [10de/036a] enabled
malTlroaci nEDnQtSePro,s :s iMzuet u1a0l9C2S,P afsrseWe[_4m8e]m _:p0t0r0 c0e0818242
 20
malloc 00162220
PCI: 00:01.3 [10de/036b] enabled
PCI: 00:02.0 [10de/036c] ops
PCI: 00:02.0 [10de/036c] enabled
PCI: 00:02.1 [10de/036d] ops
PCI: 00:02.1 [10de/036d] enabled
PCI: 00:04.0 [10de/036e] ops
PCI: 00:04.0 [10de/036e] enabled
PCI: 00:05.0 [10de/037f] ops
PCI: 00:05.0 [10de/037f] enabled
PCI: 00:05.1 [10de/037f] ops
PCI: 00:05.1 [10de/037f] enabled
PCI: 00:05.2 [10de/037f] ops
sCI: 00:05T.r2a i[n1D0QdSeP/o0s3:7 fM]u teunaalbClSePda
dsWPC[I4:8 ]0 0::00060.c0e 8[8140
 e/0370] bus ops
PCI: 00:06.0 [10de/0370] enabled
PCI: 00:06.1 [10de/0371] ops
PCI: 00:06.1 [10de/0371] enabled
PCI: 00:08.0 [10de/0373] ops
PCI: 00:08.0 [10de/0373] enabled
PCI: 00:09.0 [10de/0373] ops
PCI: 00:09.0 [10de/0373] enabled
PCI: 00:0a.0 [10de/0376] bus ops
PCI: 00:0a.0 [10de/0376] enabled
PCI: 00:0b.0 [10de/0374] bus ops
PCI: 00:0b.0 [10de/0374] enabled
PCI: 00:0c.0 [10de/0374] bus ops
:CTIr:a i0n0D:Q0ScP.o0s :[ 1M0udteu/a0l3C7S4P]a sesnWa[b4l8e]d 
000PC0Ic:e 80804:
 d.0 [10de/0378] bus ops
PCI: 00:0d.0 [10de/0378] enabled
PCI: 00:0e.0 [10de/0375] bus ops
PCI: 00:0e.0 [10de/0375] enabled
PCI: 00:0f.0 [10de/0377] bus ops
PCI: 00:0f.0 [10de/0377] enabled
scan_static_bus for PCI: 00:01.0
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
scan_static_bus for PCI: 00:01.0 done
scan_static_bus for PCI: 00:01.1
smbus: PCI: 00:01.1[0]->I2C: 01:48 disabled
smbus: PCI: 00:01.1[0]->I2C: 01:49 disabled
smbus: PCI: 00:01.1[1]->I2C: 02:51 enabled
scan_static_bus for PCI: 00:01.1 done
do_pci_scan_bridge for PCI: 00:06.0
PCI: pci_scan_bus for bus 01
malloc Enter, size 1092, free_mem_ptr 00162664
malloc 00162664
PCI: 01:05.0 [1002/515e] enabled
PCI: Static device PCI: 01:06.0 not found, disabling it.
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 02
Capability: type 0x10 @ 0x40
Capability: type 0x07 @ 0x54
PCI: 02:00.0 subordinate bus PCI-X
PCI: 02:00.0 [1033/0125] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x07 @ 0x54
PCI: 02:00.1 subordinate bus PCI-X
PCI: 02:00.1 [1033/0125] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x07 @ 0x54
do_pci_scan_bridge for PCI: 02:00.0
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
PCI: 03: 133MHz PCI-X
Capability: type 0x10 @ 0x40
Capability: type 0x07 @ 0x54
do_pci_scan_bridge for PCI: 02:00.1
PCI: pci_scan_bus for bus 04
PCI: Static device PCI: 04:04.0 not found, disabling it.
PCI: Static device PCI: 04:04.1 not found, disabling it.
PCI: pci_scan_bus returning with max=004
Capability: type 0xff @ 0xfc
Capability: type 0xff @ 0xfc
do_pci_scan_bridge returns max 4
PCI: 04: 133MHz PCI-X
PCI: pci_scan_bus returning with max=004
do_pci_scan_bridge returns max 4
do_pci_scan_bridge for PCI: 00:0b.0
PCI: pci_scan_bus for bus 05
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
do_pci_scan_bridge for PCI: 00:0c.0
PCI: pci_scan_bus for bus 06
PCI: pci_scan_bus returning with max=006
do_pci_scan_bridge returns max 6
do_pci_scan_bridge for PCI: 00:0d.0
PCI: pci_scan_bus for bus 07
PCI: pci_scan_bus returning with max=007
do_pci_scan_bridge returns max 7
do_pci_scan_bridge for PCI: 00:0e.0
PCI: pci_scan_bus for bus 08
PCI: pci_scan_bus returning with max=008
do_pci_scan_bridge returns max 8
do_pci_scan_bridge for PCI: 00:0f.0
PCI: pci_scan_bus for bus 09
PCI: pci_scan_bus returning with max=009
do_pci_scan_bridge returns max 9
PCI: pci_scan_bus returning with max=009
PCI: pci_scan_bus returning with max=009
PCI_DOMAIN: 0000 passpw: enabled
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:06.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 2 has VGA device
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:01.0 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 0 link: 0 done
PCI: 00:01.1 read_resources bus 1 link: 0
PCI: 00:01.1 read_resources bus 1 link: 0 done
PCI: 00:01.1 read_resources bus 2 link: 1
I2C: 02:51 missing read_resources
PCI: 00:01.1 read_resources bus 2 link: 1 done
PCI: 00:06.0 read_resources bus 1 link: 0
PCI: 00:06.0 read_resources bus 1 link: 0 done
PCI: 00:0a.0 read_resources bus 2 link: 0
PCI: 02:00.0 read_resources bus 3 link: 0
PCI: 02:00.0 read_resources bus 3 link: 0 done
PCI: 02:00.1 read_resources bus 4 link: 0
PCI: 02:00.1 read_resources bus 4 link: 0 done
PCI: 00:0a.0 read_resources bus 2 link: 0 done
PCI: 00:0b.0 read_resources bus 5 link: 0
PCI: 00:0b.0 read_resources bus 5 link: 0 done
PCI: 00:0c.0 read_resources bus 6 link: 0
PCI: 00:0c.0 read_resources bus 6 link: 0 done
PCI: 00:0d.0 read_resources bus 7 link: 0
PCI: 00:0d.0 read_resources bus 7 link: 0 done
PCI: 00:0e.0 read_resources bus 8 link: 0
PCI: 00:0e.0 read_resources bus 8 link: 0 done
PCI: 00:0f.0 read_resources bus 9 link: 0
PCI: 00:0f.0 read_resources bus 9 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:19.0 read_resources bus 0 link: 0
PCI: 00:19.0 read_resources bus 0 link: 0 done
PCI: 00:19.0 read_resources bus 0 link: 1
PCI: 00:19.0 read_resources bus 0 link: 1 done
PCI: 00:19.0 read_resources bus 0 link: 2
PCI: 00:19.0 read_resources bus 0 link: 2 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
   APIC: 02 links 0 child on link 0 NULL
   APIC: 03 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:18.0 links 3 child on link 0 NULL
   PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3020 flags 1 index 201c0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 20000
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 20002
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 20001
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 20004
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:01.0 links 1 child on link 0 PNP: 002e.0
    PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
     PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
     PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
     PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.a links 0 child on link 0 NULL
     PNP: 002e.b links 0 child on link 0 NULL
     PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PCI: 00:01.1 links 2 child on link 0 I2C: 01:48
    PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 10
    PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
    PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
    PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60
    PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64
    PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68
     I2C: 01:48 links 0 child on link 0 NULL
     I2C: 01:49 links 0 child on link 0 NULL
     I2C: 02:51 links 0 child on link 0 NULL
    PCI: 00:01.2 links 0 child on link 0 NULL
    PCI: 00:01.3 links 0 child on link 0 NULL
    PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 10
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:02.1 links 0 child on link 0 NULL
    PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:04.0 links 0 child on link 0 NULL
    PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24
    PCI: 00:05.1 links 0 child on link 0 NULL
    PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24
    PCI: 00:05.2 links 0 child on link 0 NULL
    PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24
    PCI: 00:06.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
    PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
     PCI: 01:05.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
     PCI: 01:06.0 links 0 child on link 0 NULL
    PCI: 00:06.1 links 0 child on link 0 NULL
    PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14
    PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 18
    PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 200 index 1c
    PCI: 00:09.0 links 0 child on link 0 NULL
    PCI: 00:09.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:09.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14
    PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 18
    PCI: 00:09.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 200 index 1c
    PCI: 00:0a.0 links 1 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 02:00.0 links 1 child on link 0 NULL
     PCI: 02:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 02:00.1 links 1 child on link 0 PCI: 04:04.0
     PCI: 02:00.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 02:00.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 02:00.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
      PCI: 04:04.0 links 0 child on link 0 NULL
      PCI: 04:04.1 links 0 child on link 0 NULL
    PCI: 00:0b.0 links 1 child on link 0 NULL
    PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:0c.0 links 1 child on link 0 NULL
    PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:0d.0 links 1 child on link 0 NULL
    PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:0e.0 links 1 child on link 0 NULL
    PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:0f.0 links 1 child on link 0 NULL
    PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
   PCI: 00:19.0 links 3 child on link 0 NULL
   PCI: 00:19.1 links 0 child on link 0 NULL
   PCI: 00:19.2 links 0 child on link 0 NULL
   PCI: 00:19.3 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:05.0 14 *  [0x0 - 0xff] io
PCI: 00:06.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 02:00.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 02:00.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:06.0 1c *  [0x0 - 0xfff] io
PCI: 00:01.1 60 *  [0x1000 - 0x10ff] io
PCI: 00:01.1 64 *  [0x1400 - 0x14ff] io
PCI: 00:01.1 68 *  [0x1800 - 0x18ff] io
PCI: 00:01.1 10 *  [0x1c00 - 0x1c3f] io
PCI: 00:01.1 20 *  [0x1c40 - 0x1c7f] io
PCI: 00:01.1 24 *  [0x1c80 - 0x1cbf] io
PCI: 00:04.0 20 *  [0x1cc0 - 0x1ccf] io
PCI: 00:05.0 20 *  [0x1cd0 - 0x1cdf] io
PCI: 00:05.1 20 *  [0x1ce0 - 0x1cef] io
PCI: 00:05.2 20 *  [0x1cf0 - 0x1cff] io
PCI: 00:05.0 10 *  [0x2000 - 0x2007] io
PCI: 00:05.0 18 *  [0x2008 - 0x200f] io
PCI: 00:05.1 10 *  [0x2010 - 0x2017] io
PCI: 00:05.1 18 *  [0x2018 - 0x201f] io
PCI: 00:05.2 10 *  [0x2020 - 0x2027] io
PCI: 00:05.2 18 *  [0x2028 - 0x202f] io
PCI: 00:08.0 14 *  [0x2030 - 0x2037] io
PCI: 00:09.0 14 *  [0x2038 - 0x203f] io
PCI: 00:05.0 14 *  [0x2040 - 0x2043] io
PCI: 00:05.0 1c *  [0x2044 - 0x2047] io
PCI: 00:05.1 14 *  [0x2048 - 0x204b] io
PCI: 00:05.1 1c *  [0x204c - 0x204f] io
PCI: 00:05.2 14 *  [0x2050 - 0x2053] io
PCI: 00:05.2 1c *  [0x2054 - 0x2057] io
PCI: 00:18.0 compute_resources_io: base: 2058 size: 3000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 20000 *  [0x0 - 0x2fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 10 *  [0x0 - 0x7ffffff] prefmem
PCI: 00:06.0 compute_resources_prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 02:00.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:06.0 24 *  [0x0 - 0x7ffffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 30 *  [0x0 - 0x1ffff] mem
PCI: 01:05.0 18 *  [0x20000 - 0x2ffff] mem
PCI: 00:06.0 compute_resources_mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 02:00.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:06.0 20 *  [0x0 - 0xfffff] mem
PCI: 00:01.3 10 *  [0x100000 - 0x13ffff] mem
PCI: 00:06.1 10 *  [0x140000 - 0x143fff] mem
PCI: 00:01.0 14 *  [0x144000 - 0x144fff] mem
PCI: 00:02.0 10 *  [0x145000 - 0x145fff] mem
PCI: 00:05.0 24 *  [0x146000 - 0x146fff] mem
PCI: 00:05.1 24 *  [0x147000 - 0x147fff] mem
PCI: 00:05.2 24 *  [0x148000 - 0x148fff] mem
PCI: 00:08.0 10 *  [0x149000 - 0x149fff] mem
PCI: 00:09.0 10 *  [0x14a000 - 0x14afff] mem
PCI: 00:02.1 10 *  [0x14b000 - 0x14b0ff] mem
PCI: 00:08.0 18 *  [0x14b100 - 0x14b1ff] mem
PCI: 00:09.0 18 *  [0x14b200 - 0x14b2ff] mem
PCI: 00:08.0 1c *  [0x14b300 - 0x14b30f] mem
PCI: 00:09.0 1c *  [0x14b310 - 0x14b31f] mem
PCI: 00:18.0 compute_resources_mem: base: 14b320 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 20002 *  [0x0 - 0x7ffffff] prefmem
PCI: 00:18.3 94 *  [0x8000000 - 0xbffffff] mem
PCI: 00:18.0 20001 *  [0xc000000 - 0xc1fffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: c200000 size: c200000 align: 27 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PNP: 002e.2
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.b
constrain_resources: PCI: 00:01.1
constrain_resources: I2C: 02:51
constrain_resources: PCI: 00:01.2
constrain_resources: PCI: 00:01.3
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:02.1
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 00:05.0
constrain_resources: PCI: 00:05.1
constrain_resources: PCI: 00:05.2
constrain_resources: PCI: 00:06.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 00:06.1
constrain_resources: PCI: 00:08.0
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 02:00.1
constrain_resources: PCI: 00:0b.0
constrain_resources: PCI: 00:0c.0
constrain_resources: PCI: 00:0d.0
constrain_resources: PCI: 00:0e.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:19.0
constrain_resources: PCI: 00:19.1
constrain_resources: PCI: 00:19.2
constrain_resources: PCI: 00:19.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
        lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
        lim->base 000c0000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 20000 *  [0x1000 - 0x3fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:06.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:01.1 60 *  [0x2000 - 0x20ff] io
Assigned: PCI: 00:01.1 64 *  [0x2400 - 0x24ff] io
Assigned: PCI: 00:01.1 68 *  [0x2800 - 0x28ff] io
Assigned: PCI: 00:01.1 10 *  [0x2c00 - 0x2c3f] io
Assigned: PCI: 00:01.1 20 *  [0x2c40 - 0x2c7f] io
Assigned: PCI: 00:01.1 24 *  [0x2c80 - 0x2cbf] io
Assigned: PCI: 00:04.0 20 *  [0x2cc0 - 0x2ccf] io
Assigned: PCI: 00:05.0 20 *  [0x2cd0 - 0x2cdf] io
Assigned: PCI: 00:05.1 20 *  [0x2ce0 - 0x2cef] io
Assigned: PCI: 00:05.2 20 *  [0x2cf0 - 0x2cff] io
Assigned: PCI: 00:05.0 10 *  [0x3000 - 0x3007] io
Assigned: PCI: 00:05.0 18 *  [0x3008 - 0x300f] io
Assigned: PCI: 00:05.1 10 *  [0x3010 - 0x3017] io
Assigned: PCI: 00:05.1 18 *  [0x3018 - 0x301f] io
Assigned: PCI: 00:05.2 10 *  [0x3020 - 0x3027] io
Assigned: PCI: 00:05.2 18 *  [0x3028 - 0x302f] io
Assigned: PCI: 00:08.0 14 *  [0x3030 - 0x3037] io
Assigned: PCI: 00:09.0 14 *  [0x3038 - 0x303f] io
Assigned: PCI: 00:05.0 14 *  [0x3040 - 0x3043] io
Assigned: PCI: 00:05.0 1c *  [0x3044 - 0x3047] io
Assigned: PCI: 00:05.1 14 *  [0x3048 - 0x304b] io
Assigned: PCI: 00:05.1 1c *  [0x304c - 0x304f] io
Assigned: PCI: 00:05.2 14 *  [0x3050 - 0x3053] io
Assigned: PCI: 00:05.2 1c *  [0x3054 - 0x3057] io
PCI: 00:18.0 allocate_resources_io: next_base: 3058 size: 3000 align: 12 gran: 12 done
PCI: 00:06.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:06.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 02:00.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 02:00.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 02:00.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 02:00.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0b.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0b.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0d.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0d.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0f.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0f.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:f0000000 size:c200000 align:27 gran:0 limit:febfffff
Assigned: PCI: 00:18.0 20002 *  [0xf0000000 - 0xf7ffffff] prefmem
Assigned: PCI: 00:18.3 94 *  [0xf8000000 - 0xfbffffff] mem
Assigned: PCI: 00:18.0 20001 *  [0xfc000000 - 0xfc1fffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc200000 size: c200000 align: 27 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:febfffff
Assigned: PCI: 00:06.0 24 *  [0xf0000000 - 0xf7ffffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done
PCI: 00:06.0 allocate_resources_prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:febfffff
Assigned: PCI: 01:05.0 10 *  [0xf0000000 - 0xf7ffffff] prefmem
PCI: 00:06.0 allocate_resources_prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done
PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 02:00.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 02:00.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 02:00.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 02:00.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0b.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0b.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0f.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:200000 align:20 gran:20 limit:febfffff
Assigned: PCI: 00:06.0 20 *  [0xfc000000 - 0xfc0fffff] mem
Assigned: PCI: 00:01.3 10 *  [0xfc100000 - 0xfc13ffff] mem
Assigned: PCI: 00:06.1 10 *  [0xfc140000 - 0xfc143fff] mem
Assigned: PCI: 00:01.0 14 *  [0xfc144000 - 0xfc144fff] mem
Assigned: PCI: 00:02.0 10 *  [0xfc145000 - 0xfc145fff] mem
Assigned: PCI: 00:05.0 24 *  [0xfc146000 - 0xfc146fff] mem
Assigned: PCI: 00:05.1 24 *  [0xfc147000 - 0xfc147fff] mem
Assigned: PCI: 00:05.2 24 *  [0xfc148000 - 0xfc148fff] mem
Assigned: PCI: 00:08.0 10 *  [0xfc149000 - 0xfc149fff] mem
Assigned: PCI: 00:09.0 10 *  [0xfc14a000 - 0xfc14afff] mem
Assigned: PCI: 00:02.1 10 *  [0xfc14b000 - 0xfc14b0ff] mem
Assigned: PCI: 00:08.0 18 *  [0xfc14b100 - 0xfc14b1ff] mem
Assigned: PCI: 00:09.0 18 *  [0xfc14b200 - 0xfc14b2ff] mem
Assigned: PCI: 00:08.0 1c *  [0xfc14b300 - 0xfc14b30f] mem
Assigned: PCI: 00:09.0 1c *  [0xfc14b310 - 0xfc14b31f] mem
PCI: 00:18.0 allocate_resources_mem: next_base: fc14b320 size: 200000 align: 20 gran: 20 done
PCI: 00:06.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:05.0 30 *  [0xfc000000 - 0xfc01ffff] mem
Assigned: PCI: 01:05.0 18 *  [0xfc020000 - 0xfc02ffff] mem
PCI: 00:06.0 allocate_resources_mem: next_base: fc030000 size: 100000 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 02:00.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 02:00.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 02:00.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 02:00.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0b.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0b.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:0f.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0f.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=00300000, basek=00000300, limitk=00200000
1: mmio_basek=00300000, basek=00400000, limitk=00500000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x2
PCI: 00:18.0 201c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 2>
PCI: 00:18.0 201b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 prefmem <node 0 link 2>
PCI: 00:18.0 201b0 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 mem <node 0 link 2>
PCI: 00:18.0 201a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 2>
PCI: 00:18.0 assign_resources, bus 0 link: 2
PCI: 00:01.0 14 <- [0x00fc144000 - 0x00fc144fff] size 0x00001000 gran 0x0c mem
PCI: 00:01.0 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PCI: 00:01.0 assign_resources, bus 0 link: 0
PCI: 00:01.1 10 <- [0x0000002c00 - 0x0000002c3f] size 0x00000040 gran 0x06 io
PCI: 00:01.1 20 <- [0x0000002c40 - 0x0000002c7f] size 0x00000040 gran 0x06 io
PCI: 00:01.1 24 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io
PCI: 00:01.1 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:01.1 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io
PCI: 00:01.1 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io
PCI: 00:01.1 assign_resources, bus 1 link: 0
PCI: 00:01.1 assign_resources, bus 1 link: 0
PCI: 00:01.1 assign_resources, bus 2 link: 1
PCI: 00:01.1 assign_resources, bus 2 link: 1
PCI: 00:01.3 10 <- [0x00fc100000 - 0x00fc13ffff] size 0x00040000 gran 0x12 mem
PCI: 00:02.0 10 <- [0x00fc145000 - 0x00fc145fff] size 0x00001000 gran 0x0c mem
PCI: 00:02.1 10 <- [0x00fc14b000 - 0x00fc14b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:04.0 20 <- [0x0000002cc0 - 0x0000002ccf] size 0x00000010 gran 0x04 io
PCI: 00:05.0 10 <- [0x0000003000 - 0x0000003007] size 0x00000008 gran 0x03 io
PCI: 00:05.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io
PCI: 00:05.0 18 <- [0x0000003008 - 0x000000300f] size 0x00000008 gran 0x03 io
PCI: 00:05.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io
PCI: 00:05.0 20 <- [0x0000002cd0 - 0x0000002cdf] size 0x00000010 gran 0x04 io
PCI: 00:05.0 24 <- [0x00fc146000 - 0x00fc146fff] size 0x00001000 gran 0x0c mem
PCI: 00:05.1 10 <- [0x0000003010 - 0x0000003017] size 0x00000008 gran 0x03 io
PCI: 00:05.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io
PCI: 00:05.1 18 <- [0x0000003018 - 0x000000301f] size 0x00000008 gran 0x03 io
PCI: 00:05.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io
PCI: 00:05.1 20 <- [0x0000002ce0 - 0x0000002cef] size 0x00000010 gran 0x04 io
PCI: 00:05.1 24 <- [0x00fc147000 - 0x00fc147fff] size 0x00001000 gran 0x0c mem
PCI: 00:05.2 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io
PCI: 00:05.2 14 <- [0x0000003050 - 0x0000003053] size 0x00000004 gran 0x02 io
PCI: 00:05.2 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io
PCI: 00:05.2 1c <- [0x0000003054 - 0x0000003057] size 0x00000004 gran 0x02 io
PCI: 00:05.2 20 <- [0x0000002cf0 - 0x0000002cff] size 0x00000010 gran 0x04 io
PCI: 00:05.2 24 <- [0x00fc148000 - 0x00fc148fff] size 0x00001000 gran 0x0c mem
PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:06.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:06.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:06.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00fc020000 - 0x00fc02ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 30 <- [0x00fc000000 - 0x00fc01ffff] size 0x00020000 gran 0x11 romem
PCI: 00:06.0 assign_resources, bus 1 link: 0
PCI: 00:06.1 10 <- [0x00fc140000 - 0x00fc143fff] size 0x00004000 gran 0x0e mem
PCI: 00:08.0 10 <- [0x00fc149000 - 0x00fc149fff] size 0x00001000 gran 0x0c mem
PCI: 00:08.0 14 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io
PCI: 00:08.0 18 <- [0x00fc14b100 - 0x00fc14b1ff] size 0x00000100 gran 0x08 mem
PCI: 00:08.0 1c <- [0x00fc14b300 - 0x00fc14b30f] size 0x00000010 gran 0x04 mem
PCI: 00:09.0 10 <- [0x00fc14a000 - 0x00fc14afff] size 0x00001000 gran 0x0c mem
PCI: 00:09.0 14 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io
PCI: 00:09.0 18 <- [0x00fc14b200 - 0x00fc14b2ff] size 0x00000100 gran 0x08 mem
PCI: 00:09.0 1c <- [0x00fc14b310 - 0x00fc14b31f] size 0x00000010 gran 0x04 mem
PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 02:00.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 02:00.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 02:00.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 02:00.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 02:00.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 mem
PCI: 02:00.1 assign_resources, bus 4 link: 0
PCI: 02:00.1 assign_resources, bus 4 link: 0
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 00:0b.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:0b.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:0b.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:0c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io
PCI: 00:0c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 00:0c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 mem
PCI: 00:0d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 07 io
PCI: 00:0d.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 07 prefmem
PCI: 00:0d.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 07 mem
PCI: 00:0e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 08 io
PCI: 00:0e.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 08 prefmem
PCI: 00:0e.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 08 mem
PCI: 00:0f.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 09 io
PCI: 00:0f.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 09 prefmem
PCI: 00:0f.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 09 mem
PCI: 00:18.0 assign_resources, bus 0 link: 2
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
   APIC: 02 links 0 child on link 0 NULL
   APIC: 03 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base f0000000 size c200000 align 27 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 31
  PCI_DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41
   PCI: 00:18.0 links 3 child on link 0 NULL
   PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 201c0
   PCI: 00:18.0 resource base f0000000 size 8000000 align 27 gran 20 limit febfffff flags 60081200 index 201b8
   PCI: 00:18.0 resource base fc000000 size 200000 align 20 gran 20 limit febfffff flags 60080200 index 201b0
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 201a8
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:01.0 links 1 child on link 0 PNP: 002e.0
    PCI: 00:01.0 resource base fc144000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
     PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
     PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
     PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.a links 0 child on link 0 NULL
     PNP: 002e.b links 0 child on link 0 NULL
     PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60
     PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PCI: 00:01.1 links 2 child on link 0 I2C: 01:48
    PCI: 00:01.1 resource base 2c00 size 40 align 6 gran 6 limit ffff flags 60000100 index 10
    PCI: 00:01.1 resource base 2c40 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
    PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit ffff flags 60000100 index 24
    PCI: 00:01.1 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 60
    PCI: 00:01.1 resource base 2400 size 100 align 8 gran 8 limit ffff flags 60000100 index 64
    PCI: 00:01.1 resource base 2800 size 100 align 8 gran 8 limit ffff flags 60000100 index 68
     I2C: 01:48 links 0 child on link 0 NULL
     I2C: 01:49 links 0 child on link 0 NULL
     I2C: 02:51 links 0 child on link 0 NULL
    PCI: 00:01.2 links 0 child on link 0 NULL
    PCI: 00:01.3 links 0 child on link 0 NULL
    PCI: 00:01.3 resource base fc100000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 10
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:02.0 resource base fc145000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 00:02.1 links 0 child on link 0 NULL
    PCI: 00:02.1 resource base fc14b000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
    PCI: 00:04.0 links 0 child on link 0 NULL
    PCI: 00:04.0 resource base 2cc0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:05.0 resource base 3000 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:05.0 resource base 3040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:05.0 resource base 3008 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:05.0 resource base 3044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:05.0 resource base 2cd0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:05.0 resource base fc146000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24
    PCI: 00:05.1 links 0 child on link 0 NULL
    PCI: 00:05.1 resource base 3010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:05.1 resource base 3048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:05.1 resource base 3018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:05.1 resource base 304c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:05.1 resource base 2ce0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:05.1 resource base fc147000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24
    PCI: 00:05.2 links 0 child on link 0 NULL
    PCI: 00:05.2 resource base 3020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:05.2 resource base 3050 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:05.2 resource base 3028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:05.2 resource base 3054 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:05.2 resource base 2cf0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:05.2 resource base fc148000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24
    PCI: 00:06.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:06.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:06.0 resource base f0000000 size 8000000 align 27 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:06.0 resource base fc000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base f0000000 size 8000000 align 27 gran 27 limit febfffff flags 60001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
     PCI: 01:05.0 resource base fc020000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 18
     PCI: 01:05.0 resource base fc000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
     PCI: 01:06.0 links 0 child on link 0 NULL
    PCI: 00:06.1 links 0 child on link 0 NULL
    PCI: 00:06.1 resource base fc140000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:08.0 resource base fc149000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 00:08.0 resource base 3030 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
    PCI: 00:08.0 resource base fc14b100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 18
    PCI: 00:08.0 resource base fc14b300 size 10 align 4 gran 4 limit febfffff flags 60000200 index 1c
    PCI: 00:09.0 links 0 child on link 0 NULL
    PCI: 00:09.0 resource base fc14a000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 00:09.0 resource base 3038 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
    PCI: 00:09.0 resource base fc14b200 size 100 align 8 gran 8 limit febfffff flags 60000200 index 18
    PCI: 00:09.0 resource base fc14b310 size 10 align 4 gran 4 limit febfffff flags 60000200 index 1c
    PCI: 00:0a.0 links 1 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 02:00.0 links 1 child on link 0 NULL
     PCI: 02:00.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 02:00.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
     PCI: 02:00.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 02:00.1 links 1 child on link 0 PCI: 04:04.0
     PCI: 02:00.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 02:00.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
     PCI: 02:00.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
      PCI: 04:04.0 links 0 child on link 0 NULL
      PCI: 04:04.1 links 0 child on link 0 NULL
    PCI: 00:0b.0 links 1 child on link 0 NULL
    PCI: 00:0b.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0b.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0b.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 00:0c.0 links 1 child on link 0 NULL
    PCI: 00:0c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 00:0d.0 links 1 child on link 0 NULL
    PCI: 00:0d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0d.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0d.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 00:0e.0 links 1 child on link 0 NULL
    PCI: 00:0e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 00:0f.0 links 1 child on link 0 NULL
    PCI: 00:0f.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0f.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:0f.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94
   PCI: 00:19.0 links 3 child on link 0 NULL
   PCI: 00:19.1 links 0 child on link 0 NULL
   PCI: 00:19.2 links 0 child on link 0 NULL
   PCI: 00:19.3 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:00.0 subsystem <- 15d9/1511
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 15d9/1511
PCI: 00:01.0 cmd <- 0f
mcp55 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
w83627hf hwm smbus enabled
mcp55 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297
PCI: 00:01.1 subsystem <- 15d9/1511
PCI: 00:01.1 cmd <- 01
PCI: 00:01.2 cmd <- 400
PCI: 00:01.3 cmd <- 02
PCI: 00:02.0 subsystem <- 15d9/1511
PCI: 00:02.0 cmd <- 02
PCI: 00:02.1 subsystem <- 15d9/1511
PCI: 00:02.1 cmd <- 02
PCI: 00:04.0 subsystem <- 15d9/1511
PCI: 00:04.0 cmd <- 01
PCI: 00:05.0 subsystem <- 15d9/1511
PCI: 00:05.0 cmd <- 03
PCI: 00:05.1 subsystem <- 15d9/1511
PCI: 00:05.1 cmd <- 03
PCI: 00:05.2 subsystem <- 15d9/1511
PCI: 00:05.2 cmd <- 03
PCI: 00:06.0 bridge ctrl <- 0a0b
PCI: 00:06.0 cmd <- 107
PCI: 01:05.0 cmd <- 83
PCI: 00:06.1 subsystem <- 15d9/1511
PCI: 00:06.1 cmd <- 02
PCI: 00:08.0 subsystem <- 15d9/1511
PCI: 00:08.0 cmd <- 03
PCI: 00:09.0 subsystem <- 15d9/1511
PCI: 00:09.0 cmd <- 03
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 00
PCI: 02:00.0 bridge ctrl <- 0003
PCI: 02:00.0 cmd <- 00
PCI: 02:00.1 bridge ctrl <- 0003
PCI: 02:00.1 cmd <- 00
PCI: 00:0b.0 bridge ctrl <- 0003
PCI: 00:0b.0 cmd <- 00
PCI: 00:0c.0 bridge ctrl <- 0003
PCI: 00:0c.0 cmd <- 00
PCI: 00:0d.0 bridge ctrl <- 0003
PCI: 00:0d.0 cmd <- 00
PCI: 00:0e.0 bridge ctrl <- 0003
PCI: 00:0e.0 cmd <- 00
PCI: 00:0f.0 bridge ctrl <- 0003
PCI: 00:0f.0 cmd <- 00
PCI: 00:18.1 subsystem <- 15d9/1511
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 15d9/1511
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:19.0 cmd <- 00
PCI: 00:19.1 cmd <- 00
PCI: 00:19.2 cmd <- 00
PCI: 00:19.3 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x0000c000, offset=0x00100000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 40f12
CPU: family 0f, model 41, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model Dual-Core AMD Opteron(tm) Processor 2212
Setting up local apic... apic_id: 0x00 done.
Clearing memory 2048K - 2097152K: ------------------------------- done
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: vendor AMD device 40f12
CPU: family 0f, model 41, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model Dual-Core AMD Opteron(tm) Processor 2212
Setting up local apic... apic_id: 0x01 done.
CPU #1 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 2.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #2
CPU: vendor AMD device 40f12
CPU: family 0f, model 41, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model Dual-Core AMD Opteron(tm) Processor 2212
Setting up local apic... apic_id: 0x02 done.
Clearing memory 2097152K - 5242880K: ----------------++++++++++++++++ done
CPU #2 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #3
Waiting for 1 CPUS to stop
CPU: vendor AMD device 40f12
CPU: family 0f, model 41, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model Dual-Core AMD Opteron(tm) Processor 2212
Setting up local apic... apic_id: 0x03 done.
CPU #3 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:01.0 init
IOAPIC: Initializing IOAPIC at 0xfc144000
IOAPIC: Bootstrap Processor Local APIC = 00
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
set power on after power fail
RTC Init
Invalid CMOS LB checksum
enabling HPET @0xfed00000
PNP: 002e.2 init
PNP: 002e.5 init
Keyboard init...
Keyboard controller output buffer result timeout
PNP: 002e.b init
PCI: 00:01.1 init
PCI: 00:02.1 init
PCI: 00:04.0 init
IDE0
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci10de,036e.rom
PCI: 00:05.0 init
SATA S  SATA P 
PCI: 00:05.1 init
SATA S  SATA P 
PCI: 00:05.2 init
SATA S  SATA P 
PCI: 00:06.0 init
PCI DOMAIN mem base = 0x00f0000000
[0x50] <-- 0xf0000000
PCI: 00:06.1 init
Azalia: codec type: Azalia
Azalia: base = fc140000
Azalia: codec_mask = 01
Azalia: Initializing codec #0
PCI: 00:08.0 init
MCP55 MAC PHY ID 0x01410c00 PHY ADDR 2
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci10de,0373.rom
PCI: 00:09.0 init
MCP55 MAC PHY ID 0x01410c00 PHY ADDR 3
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci10de,0373.rom
PCI: 00:0a.0 init
PCI: 00:0b.0 init
PCI: 00:0c.0 init
PCI: 00:0d.0 init
PCI: 00:0e.0 init
PCI: 00:0f.0 init
PCI: 00:18.1 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:18.2 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:19.0 init
PCI: 00:19.1 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:19.2 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:19.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:01.2 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci10de,036a.rom
PCI: 00:01.3 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000
Check 
CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000
CBFS:  Could not find file pci10de,036b.rom
PCI: 01:05.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0
Check pci1002,515e.rom
In cbfs, rom address for PCI: 01:05.0 = fff14ff8
PCI Expansion ROM, signature 0xaa55, INIT size 0xb000, data ptr 0x0158
PCI ROM Image, Vendor 1002, Device 515e,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff14ff8 to 0xc0000, 0xb000 bytes
Real mode stub @00000600: 609 bytes
Calling Option ROM...
oprom: INT# 0x10
oprom: eax: 00000007 ebx: 00000200 ecx: 00000000 edx: 000003c2
oprom: ebp: 0015ff10 esp: 00000fca edi: 00000000 esi: 0000597b
oprom:  ip: 481c      cs: c000   flags: 00000006
Unsupported software interrupt #0x10
int10 call returned error.
... Option ROM returned.
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 6 resources
PCI: 00:18.0: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 4 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 3 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.5: enabled 1, 4 resources
PNP: 002e.6: enabled 0, 3 resources
PNP: 002e.7: enabled 0, 3 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 2 resources
PCI: 00:01.1: enabled 1, 6 resources
I2C: 01:48: enabled 0, 0 resources
I2C: 01:49: enabled 0, 0 resources
I2C: 02:51: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 1 resources
PCI: 00:02.1: enabled 1, 1 resources
PCI: 00:04.0: enabled 1, 1 resources
PCI: 00:05.0: enabled 1, 6 resources
PCI: 00:05.1: enabled 1, 6 resources
PCI: 00:05.2: enabled 1, 6 resources
PCI: 00:06.0: enabled 1, 3 resources
PCI: 01:06.0: enabled 0, 0 resources
PCI: 00:06.1: enabled 1, 1 resources
PCI: 00:08.0: enabled 1, 4 resources
PCI: 00:09.0: enabled 1, 4 resources
PCI: 00:0a.0: enabled 1, 3 resources
PCI: 02:00.0: enabled 1, 3 resources
PCI: 02:00.1: enabled 1, 3 resources
PCI: 04:04.0: enabled 0, 0 resources
PCI: 04:04.1: enabled 0, 0 resources
PCI: 00:0b.0: enabled 1, 3 resources
PCI: 00:0c.0: enabled 1, 3 resources
PCI: 00:0d.0: enabled 1, 3 resources
PCI: 00:0e.0: enabled 1, 3 resources
PCI: 00:0f.0: enabled 1, 3 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
APIC: 01: enabled 1, 0 resources
PCI: 00:19.0: enabled 1, 0 resources
PCI: 00:19.1: enabled 1, 0 resources
PCI: 00:19.2: enabled 1, 0 resources
PCI: 00:19.3: enabled 1, 0 resources
APIC: 02: enabled 1, 0 resources
APIC: 03: enabled 1, 0 resources
PCI: 00:01.2: enabled 1, 0 resources
PCI: 00:01.3: enabled 1, 1 resources
PCI: 01:05.0: enabled 1, 4 resources
Initializing CBMEM area to 0x7fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 7fff0200...ok
High Tables Base is 7fff0000.
Writing IRQ routing tables to 0xf0000...done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x7fff0400...done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f06b4
Adding CBMEM entry as no. 3
Wrote the mp table end at: 7fff1410 - 7fff16b4
MP table: 692 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 5bdf
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x7fff2400
rom_table_end = 0x7fff2400
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x7fff2400 to 0x80000000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000007ffeffff: RAM
 3. 000000007fff0000-000000007fffffff: CONFIGURATION TABLES
 4. 0000000080000000-00000000bfffffff: RAM
 5. 0000000100000000-000000013fffffff: RAM
Wrote coreboot table at: 7fff2400 - 7fff2cd0  checksum 8b9a
coreboot table: 2256 bytes.
 0. FREE SPACE 7fff4400 0000bc00
 1. GDT        7fff0200 00000200
 2. IRQ TABLE  7fff0400 00001000
 3. SMP TABLE  7fff1400 00001000
 4. COREBOOT   7fff2400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff0b1b8
  data (compression=1)
malloc Enter, size 36, free_mem_ptr 00162aa8
malloc 00162aa8
  New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfff0b1f0 filesize 0x9dc3
  (cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfff0b1f0 filesize 0x9dc3
Loading segment from rom address 0xfff0b1d4
  Entry Point 0x000fdf82
Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3
lb: [0x0000000000100000, 0x0000000000164000)
Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3
using LZMA
[ 0x00000000000ec400, 0000000000100000, 0x0000000000100000) <- 00000000fff0b1f0
dest 000ec400, end 00100000, bouncebuffer bff38000
Loaded segments
Jumping to boot code at fdf82
entry    = 0x000fdf82
lb_start = 0x00100000
lb_size  = 0x00064000
adjust   = 0xbfe9c000
buffer   = 0xbff38000
     elf_boot_notes = 0x001154a0
adjusted_boot_notes = 0xbffb14a0
Start bios (version 0.6.0-20100326_214650-morn.localdomain)
Found mainboard Supermicro H8DME-2
Found CBFS header at 0xfffeffe0
Ram Size=0xc0000000 (0x0000000040000000 high)
CPU Mhz=2000
Found 4 cpu(s) max supported 4 cpu(s)
Copying PIR from 0x7fff0400 to 0x000f7b80
Copying MPTABLE from 0x7fff1400/7fff1410 to 0x000f78c0
SMBIOS ptr=0x000f78a0 table=0xbffffe70
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga console
Starting SeaBIOS (version 0.6.0-20100326_214650-morn.localdomain)

EHCI init on dev 00:02.1 (regs=0xfc14b020)
Found 0 lpt ports
Found 1 serial ports
ATA controller 0 at 1f0/3f4/0 (irq 14 dev 20)
ATA controller 1 at 170/374/0 (irq 15 dev 20)
ATA controller 2 at 3000/3040/0 (irq 0 dev 28)
ata0-0: SONY    DVD RW DRU-840A ATAPI-7 CD-Rom/DVD-Rom
ATA controller 3 at 3008/3044/0 (irq 0 dev 28)
ATA controller 4 at 3010/3048/0 (irq 0 dev 29)
ATA controller 5 at 3018/304c/0 (irq 0 dev 29)
ATA controller 6 at 3020/3050/0 (irq 0 dev 2a)
ATA controller 7 at 3028/3054/0 (irq 0 dev 2a)
ata2-0: WDC WD1601ABYS-01C0A0 ATA-8 Hard-Disk (153 GiBytes)
drive 0x000f7790: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=321672960
PS2 keyboard initialized
Scan for option roms
Press F12 for boot menu.

Returned 61440 bytes of ZoneHigh
e820 map has 8 items:
  0: 0000000000000000 - 000000000009f400 = 1
  1: 000000000009f400 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000007fff0000 = 1
  4: 000000007fff0000 - 0000000080000000 = 2
  5: 0000000080000000 - 00000000bffff000 = 1
  6: 00000000bffff000 - 00000000c0000000 = 2
  7: 0000000100000000 - 0000000140000000 = 1
enter handle_19:
  NULL
Booting from Floppy...
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CD-Rom...
Device reports MEDIUM NOT PRESENT
atapi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
Stefan Reinauer - 2010-05-14 11:17:11
On 5/13/10 6:56 PM, Joe Korty wrote:
> On Thu, May 13, 2010 at 11:40:36AM -0400, Stefan Reinauer wrote:
>   
>> On 5/13/10 5:08 PM, Joe Korty wrote:
>>     
>>> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote:
>>>   
>>>       
>>>> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a
>>>> while ago and now I ported my version of the Azalia code to MCP55 /
>>>> H8DME (assuming that's the board target you use for the H8DME-2)
>>>> Can you please see if this is any better than before? It's likely that
>>>> the verb table won't match the codec used on that board, but there only
>>>> was a single codec in the mcp55 driver and the used codec is usually
>>>> mainboard dependent, not chipset dependent.
>>>>         
>>>     
>>> It works!!!
>>> But I didn't hear a beep during coreboot.  Was I supposed to?
>>>       
>> No, no beeps... The driver just initializes the codec.
>>
>> If someone had a nice piece of code to output a sample on azalia
>> devices, I think we should make it an option. I looked at alsa some time
>> ago but found it less than trivial to extract the info useful for us.
>>
>> Could you please send a log file containing the output of the new azalia
>> driver?
>>     
> Sure.  Here it is....
> Regards,
> Joe
>   
> PCI: 00:06.1 init
> Azalia: codec type: Azalia
> Azalia: base = fc140000
> Azalia: codec_mask = 01
> Azalia: Initializing codec #0
> PCI: 00:08.0 init
>   
It's still timing out though, despite the fact that it knows there is a
codec.

Does sound work?
Joe Korty - 2010-05-14 14:29:28
On Fri, May 14, 2010 at 07:17:11AM -0400, Stefan Reinauer wrote:
> >> Could you please send a log file containing the output of the new azalia
> >> driver?
> >   
> > PCI: 00:06.1 init
> > Azalia: codec type: Azalia
> > Azalia: base = fc140000
> > Azalia: codec_mask = 01
> > Azalia: Initializing codec #0
> > PCI: 00:08.0 init
> >   
> It's still timing out though, despite the fact that it knows there is a
> codec.
> 
> Does sound work?


Hi Stefan,
Believe it or not, I see no audio-out port on the back of
the motherboard.  The H8DME-2's manual does not show one
on its schematic, and a grep of the text shows no mention
of audio output capabilities.

I never noticed this until now, since I have no interest
in audio in any of my projects.

Joe

PS: I'm curious, why does coreboot need to initialize
the audio?  It has no need of audio itself, and AFAIK,
no payload which follows coreboot needs audio either.
I believe that if coreboot restricted itself to
initializing only that which was absolutely essential,
it would become intrinsically more stable.
Stefan Reinauer - 2010-05-14 14:45:54
On 5/14/10 4:29 PM, Joe Korty wrote:
> PS: I'm curious, why does coreboot need to initialize
> the audio?  It has no need of audio itself, and AFAIK,
> no payload which follows coreboot needs audio either.
>   
The wiring of the codec is mainboard specific and all Windows and Linux
drivers expect the BIOS to set up the Azalia codecs, or sound will not
work correctly. This is not something that could be probed by the OS
otherwise.

> I believe that if coreboot restricted itself to
> initializing only that which was absolutely essential,
> it would become intrinsically more stable.
>   
Oh, that is absolutely what we do. If the mainboard porters care to do
their job right. However many people assume that they don't have to
worry since they don't use a certain feature for their project and just
leave it as it is.

Stefan
Peter Stuge - 2010-05-14 18:05:16
Joe Korty wrote:
> > Does sound work?
> 
> Hi Stefan,
> Believe it or not, I see no audio-out port on the back of
> the motherboard.  The H8DME-2's manual does not show one
> on its schematic, and a grep of the text shows no mention
> of audio output capabilities.
> 
> I never noticed this until now, since I have no interest
> in audio in any of my projects.

In order to help improve coreboot, could you try to load the right
audio drivers for azalia and see what ends up in the kernel log?


//Peter

Patch

Index: src/mainboard/supermicro/h8dme/hda_verb.h
===================================================================
--- src/mainboard/supermicro/h8dme/hda_verb.h	(revision 0)
+++ src/mainboard/supermicro/h8dme/hda_verb.h	(revision 0)
@@ -0,0 +1,99 @@ 
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2004 Tyan Computer
+ * Copyright (C) 2006-2007 AMD
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+static u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0880,	// Codec Vendor ID / Device ID
+	0x00000000,	// Subsystem ID
+	0x0000000d,	// Number of jacks
+
+	/* HDA Codec Subsystem ID Verb Table: 0x0000e601 */
+	0x00172001,
+	0x001721e6,
+	0x00172200,
+	0x00172300,
+
+	0x01471c10,
+	0x01471d44,
+	0x01471e01,
+	0x01471f01,
+	// 1
+	0x01571c12,
+	0x01571d14,
+	0x01571e01,
+	0x01571f01,
+	// 2
+	0x01671c11,
+	0x01671d60,
+	0x01671e01,
+	0x01671f01,
+	// 3
+	0x01771c14,
+	0x01771d20,
+	0x01771e01,
+	0x01771f01,
+	// 4
+	0x01871c30,
+	0x01871d9c,
+	0x01871ea1,
+	0x01871f01,
+	// 5
+	0x01971c40,
+	0x01971d9c,
+	0x01971ea1,
+	0x01971f02,
+	// 6
+	0x01a71c31,
+	0x01a71d34,
+	0x01a71e81,
+	0x01a71f01,
+	// 7
+	0x01b71c1f,
+	0x01b71d44,
+	0x01b71e21,
+	0x01b71f02,
+	// 8
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	// 9
+	0x01d71c3e,
+	0x01d71d01,
+	0x01d71e83,
+	0x01d71f99,
+	// 10
+	0x01e71c20,
+	0x01e71d41,
+	0x01e71e45,
+	0x01e71f01,
+	// 11
+	0x01f71c50,
+	0x01f71d91,
+	0x01f71ec5,
+	0x01f71f01,
+};
+
+extern u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
Index: src/mainboard/supermicro/h8dme/mainboard.c
===================================================================
--- src/mainboard/supermicro/h8dme/mainboard.c	(revision 5543)
+++ src/mainboard/supermicro/h8dme/mainboard.c	(working copy)
@@ -1,6 +1,9 @@ 
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2007-2009 Advanced Micro Devices
+ * Copyright (C) 2010 coresystems GmbH
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -17,8 +20,22 @@ 
  */
 
 #include <device/device.h>
+#include "hda_verb.h"
 #include "chip.h"
 
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev) 
+{
+	verb_setup();
+}
+
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Supermicro H8DME Mainboard")
+	.enable_dev = mainboard_enable,
 };
+
Index: src/southbridge/nvidia/mcp55/Makefile.inc
===================================================================
--- src/southbridge/nvidia/mcp55/Makefile.inc	(revision 5543)
+++ src/southbridge/nvidia/mcp55/Makefile.inc	(working copy)
@@ -1,5 +1,5 @@ 
 driver-y += mcp55.o
-driver-y += mcp55_aza.o
+driver-y += mcp55_azalia.o
 driver-y += mcp55_ht.o
 driver-y += mcp55_ide.o
 driver-y += mcp55_lpc.o
Index: src/southbridge/nvidia/mcp55/mcp55_azalia.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_azalia.c	(revision 0)
+++ src/southbridge/nvidia/mcp55/mcp55_azalia.c	(revision 0)
@@ -0,0 +1,297 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "mcp55.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 reg32;
+	int count;
+
+	/* Write (val & mask) to port */
+	val &= mask;
+	reg32 = read32(port);
+	reg32 &= ~mask;
+	reg32 |= val;
+	write32(port, reg32);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		reg32 = read32(port);
+		reg32 &= mask;
+	} while ((reg32 != val) && --count);
+
+	/* Timeout occured */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static int codec_detect(u32 base)
+{
+	u32 reg32;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Read in Codec location (BAR + 0xe)[2..0]*/
+	reg32 = read32(base + 0xe);
+	reg32 &= 0x0f;
+	if (!reg32)
+		goto no_codec;
+
+	return reg32;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
+	return 0;
+}
+
+u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
+
+static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
+{
+	int idx=0;
+
+	while (idx < (cim_verb_data_size / sizeof(u32))) {
+		u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+		if (cim_verb_data[idx] != viddid) {
+			idx += verb_size + 3; // skip verb + header
+			continue;
+		}
+		*verb = &cim_verb_data[idx+3];
+		return verb_size;
+	}
+
+	/* Not all codecs need to load another verb */
+	return 0;
+}
+
+/**
+ *  Wait 50usec for for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 reg32 = read32(base +  HDA_ICII_REG);
+		if (!(reg32 & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+
+static int wait_for_valid(u32 base)
+{
+	u32 reg32;
+
+	/* Send the verb to the codec */
+	reg32 = read32(base + 0x68);
+	reg32 |= (1 << 0) | (1 << 1);
+	write32(base + 0x68, reg32);
+
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		reg32 = read32(base + HDA_ICII_REG);
+		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+static void codec_init(struct device *dev, u32 base, int addr)
+{
+	u32 reg32;
+	u32 *verb;
+	u32 verb_size;
+	int i;
+
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	reg32 = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, reg32);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	reg32 = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
+	verb_size = find_verb(dev, reg32, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
+
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
+}
+
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(dev, base, i);
+	}
+}
+
+static void azalia_init(struct device *dev)
+{
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	u8 reg8;
+	u32 reg32;
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	pci_write_config8(dev, 0x3c, 0x0a); // unused?
+
+	reg8 = pci_read_config8(dev, 0x40);
+	reg8 |= (1 << 3); // Clear Clock Detect Bit
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 |= (1 << 2); // Enable clock detection
+	pci_write_config8(dev, 0x40, reg8);
+	mdelay(1);
+	reg8 = pci_read_config8(dev, 0x40);
+	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
+
+	//
+	reg8 = pci_read_config8(dev, 0x40); // Audio Control
+	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+	pci_write_config8(dev, 0x40, reg8);
+
+	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
+	reg8 &= ~(1 << 7); // Docking not supported
+	pci_write_config8(dev, 0x4d, reg8);
+
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	// NOTE this will break as soon as the Azalia get's a bar above
+	// 4G. Is there anything we can do about it?
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
+		codecs_init(dev, base, codec_mask);
+	}
+}
+
+static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations azalia_pci_ops = {
+	.set_subsystem    = azalia_set_subsystem,
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= azalia_init,
+	.scan_bus		= 0,
+//	.enable			= mcp55_enable,
+	.ops_pci		= &azalia_pci_ops,
+};
+
+static const struct pci_driver azalia __pci_driver = {
+	.ops	= &azalia_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
+};
+
Index: src/southbridge/nvidia/mcp55/mcp55_aza.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_aza.c	(revision 5543)
+++ src/southbridge/nvidia/mcp55/mcp55_aza.c	(working copy)
@@ -1,269 +0,0 @@ 
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <delay.h>
-#include "mcp55.h"
-
-static int set_bits(u32 port, u32 mask, u32 val)
-{
-	u32 dword;
-	int count;
-
-	val &= mask;
-	dword = read32(port);
-	dword &= ~mask;
-	dword |= val;
-	write32(port, dword);
-
-	count = 50;
-	do {
-		dword = read32(port);
-		dword &= mask;
-		udelay(100);
-	} while ((dword != val) && --count);
-
-	if(!count) return -1;
-
-	udelay(540);
-	return 0;
-
-}
-
-static int codec_detect(u32 base)
-{
-	u32 dword;
-
-	/* 1 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 2 */
-	dword = read32(base + 0x0e);
-	dword |= 7;
-	write32(base + 0x0e, dword);
-
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
-
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 5 */
-	dword = read32(base + 0xe);
-	dword &= 7;
-
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk(BIOS_DEBUG, "No codec!\n");
-		return 0;
-	}
-	return dword;
-
-}
-
-/* FIXME this should go to the mainboard code */
-static u32 verb_data[] = {
-#if 0
-	0x00172001,
-	0x001721e6,
-	0x00172200,
-	0x00172300,
-#endif
-
-	0x01471c10,
-	0x01471d44,
-	0x01471e01,
-	0x01471f01,
-//1
-	0x01571c12,
-	0x01571d14,
-	0x01571e01,
-	0x01571f01,
-//2
-	0x01671c11,
-	0x01671d60,
-	0x01671e01,
-	0x01671f01,
-//3
-	0x01771c14,
-	0x01771d20,
-	0x01771e01,
-	0x01771f01,
-//4
-	0x01871c30,
-	0x01871d9c,
-	0x01871ea1,
-	0x01871f01,
-//5
-	0x01971c40,
-	0x01971d9c,
-	0x01971ea1,
-	0x01971f02,
-//6
-	0x01a71c31,
-	0x01a71d34,
-	0x01a71e81,
-	0x01a71f01,
-//7
-	0x01b71c1f,
-	0x01b71d44,
-	0x01b71e21,
-	0x01b71f02,
-//8
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-//9
-	0x01d71c3e,
-	0x01d71d01,
-	0x01d71e83,
-	0x01d71f99,
-//10
-	0x01e71c20,
-	0x01e71d41,
-	0x01e71e45,
-	0x01e71f01,
-//11
-	0x01f71c50,
-	0x01f71d91,
-	0x01f71ec5,
-	0x01f71f01,
-};
-
-static unsigned find_verb(u32 viddid, u32 **verb)
-{
-	if(viddid != 0x10ec0880) return 0;
-	*verb =  (u32 *)verb_data;
-	return sizeof(verb_data)/sizeof(u32);
-}
-
-
-static void codec_init(u32 base, int addr)
-{
-	u32 dword;
-	u32 *verb;
-	unsigned verb_size;
-	int i;
-
-	/* 1 */
-	do {
-		dword = read32(base + 0x68);
-	} while (dword & 1);
-
-	dword = (addr<<28) | 0x000f0000;
-	write32(base + 0x60, dword);
-
-	do {
-		dword = read32(base + 0x68);
-	} while ((dword & 3)!=2);
-
-	dword = read32(base + 0x64);
-
-	/* 2 */
-	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
-	verb_size = find_verb(dword, &verb);
-
-	if(!verb_size) {
-		printk(BIOS_DEBUG, "No verb!\n");
-		return;
-	}
-
-	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
-	/* 3 */
-	for(i=0; i<verb_size; i++) {
-		do {
-			dword = read32(base + 0x68);
-		} while (dword & 1);
-
-		write32(base + 0x60, verb[i]);
-
-		do {
-			dword = read32(base + 0x68);
-		} while ((dword & 3) != 2);
-	}
-	printk(BIOS_DEBUG, "verb loaded!\n");
-}
-
-static void codecs_init(u32 base, u32 codec_mask)
-{
-	int i;
-	for(i=2; i>=0; i--) {
-		if( codec_mask & (1<<i) )
-			codec_init(base, i);
-	}
-}
-
-static void aza_init(struct device *dev)
-{
-	u32 base;
-	struct resource *res;
-	u32 codec_mask;
-
-	res = find_resource(dev, 0x10);
-	if(!res)
-		return;
-
-	base = res->base;
-	printk(BIOS_DEBUG, "base = 0x%08x\n", base);
-
-	codec_mask = codec_detect(base);
-
-	if(codec_mask) {
-		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
-		codecs_init(base, codec_mask);
-	}
-}
-
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem	= lpci_set_subsystem,
-};
-
-static struct device_operations aza_audio_ops  = {
-	.read_resources	= pci_dev_read_resources,
-	.set_resources	= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-//	.enable		= mcp55_enable,
-	.init		= aza_init,
-	.scan_bus	= 0,
-	.ops_pci	= &lops_pci,
-};
-
-static const struct pci_driver azaaudio_driver __pci_driver = {
-	.ops	= &aza_audio_ops,
-	.vendor	= PCI_VENDOR_ID_NVIDIA,
-	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
-};
-