Patchwork FILO 2.6.31

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Submitter Stefan Reinauer
Date 2010-05-19 20:29:21
Message ID <4BF44A21.5080606@coresystems.de>
Download mbox | patch
Permalink /patch/1360/
State Not Applicable
Headers show

Comments

Stefan Reinauer - 2010-05-19 20:29:21
Hi,

I cleaned up the structures used for Linux booting in FILO, to match
what Linux uses these days and moved the structure definitions to a
separate (include) file.
Also fill in 16MB alignment to fix 2.6.31.. untested...

Best regards,
Stefan
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Joop Boonen - 2010-05-19 22:02:12
On Wed, May 19, 2010 10:29 pm, Stefan Reinauer wrote:
> Hi,
>
> I cleaned up the structures used for Linux booting in FILO, to match
> what Linux uses these days and moved the structure definitions to a
> separate (include) file.
> Also fill in 16MB alignment to fix 2.6.31.. untested...

I've just tested the patch. It looks like it works perfectly.

I've attached the session log.

It only fails because the sil3114 driver isn't loaded it's in the initrd
file.

I didn't find the option how to define initrd in the filo command line.

>
> Best regards,
> Stefan
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


coreboot-4.0-r5573 Wed May 19 23:04:29 CEST 2010 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid: 
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
ht reset -


coreboot-4.0-r5573 Wed May 19 23:04:29 CEST 2010 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid: 
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
Interleaved
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
Interleaved
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
ECC enabled
ECC enabled
Initializing memory:  done
Initializing memory:  done
Ram4
v_esp=000cee28
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (409600 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r5573 Wed May 19 23:04:29 CEST 2010 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 0, 0 resources
PCI: 00:01.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 0, 0 resources
PNP: 002e.6: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:01.2: enabled 1, 0 resources
PCI: 00:01.3: enabled 1, 0 resources
I2C: 00:70: enabled 1, 0 resources
I2C: 00:2c: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
I2C: 00:54: enabled 1, 0 resources
I2C: 00:55: enabled 1, 0 resources
I2C: 00:56: enabled 1, 0 resources
I2C: 00:57: enabled 1, 0 resources
PCI: 00:01.5: enabled 0, 0 resources
PCI: 00:01.6: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:00.1: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.1: enabled 1, 0 resources
    PCI: 00:00.2: enabled 0, 0 resources
    PCI: 00:01.0: enabled 0, 0 resources
    PCI: 00:06.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 0, 2 resources
    PNP: 002e.2: enabled 0, 2 resources
    PNP: 002e.3: enabled 1, 2 resources
    PNP: 002e.4: enabled 0, 0 resources
    PNP: 002e.5: enabled 0, 0 resources
    PNP: 002e.6: enabled 1, 3 resources
    PNP: 002e.7: enabled 0, 0 resources
    PNP: 002e.8: enabled 0, 0 resources
    PNP: 002e.9: enabled 0, 0 resources
    PNP: 002e.a: enabled 0, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:01.2: enabled 1, 0 resources
   PCI: 00:01.3: enabled 1, 0 resources
    I2C: 00:70: enabled 1, 0 resources
     I2C: 00:2c: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
    I2C: 00:54: enabled 1, 0 resources
    I2C: 00:55: enabled 1, 0 resources
    I2C: 00:56: enabled 1, 0 resources
    I2C: 00:57: enabled 1, 0 resources
   PCI: 00:01.5: enabled 0, 0 resources
   PCI: 00:01.6: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
malloc Enter, size 1092, free_mem_ptr 00160000
malloc 00160000
PCI: 00:19.0 [1022/1100] bus ops
PCI: 00:19.0 [1022/1100] enabled
malloc Enter, size 1092, free_mem_ptr 00160444
malloc 00160444
PCI: 00:19.1 [1022/1101] enabled
malloc Enter, size 1092, free_mem_ptr 00160888
malloc 00160888
PCI: 00:19.2 [1022/1102] enabled
malloc Enter, size 1092, free_mem_ptr 00160ccc
malloc 00160ccc
PCI: 00:19.3 [1022/1103] ops
PCI: 00:19.3 [1022/1103] enabled
  PCI: 00:19.3 siblings=0
malloc Enter, size 1092, free_mem_ptr 00161110
malloc 00161110
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] enabled
PCI: Using configuration type 1
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
flags: 0x8000
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
Capability: type 0x08 @ 0xc0
flags: 0x0041
Collapsing PCI: 00:01.0 [1022/7450]
Capability: type 0x08 @ 0xc0
flags: 0x0083
Collapsing PCI: 00:03.0 [1022/7460]
Capability: type 0x08 @ 0x80
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
Capability: type 0x08 @ 0xc0
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
Capability: type 0x08 @ 0xc0
Capability: type 0x08 @ 0x80
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
Capability: type 0x08 @ 0xc0
flags: 0x2101
Capability: type 0x08 @ 0x80
Capability: type 0x08 @ 0xa0
Capability: type 0x08 @ 0xc0
PCI: 00:00.0 [1022/7450] bus ops
PCI: 00:00.0 [1022/7450] enabled
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
flags: 0x8000
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
Capability: type 0x08 @ 0xc0
flags: 0x0040
PCI: 00:01.0 count: 0002 static_count: 0002
PCI: 00:01.0 [1022/7450] enabled next_unitid: 0003
PCI: 00:00.0 [1022/7460] bus ops
PCI: 00:00.0 [1022/7460] enabled
Capability: type 0x08 @ 0xc0
flags: 0x0080
PCI: 00:03.0 count: 0004 static_count: 0002
PCI: 00:03.0 [1022/7460] enabled next_unitid: 0007
PCI: pci_scan_bus for bus 00
PCI: 00:01.0 [1022/7450] enabled
PCI: 00:01.1 [1022/7451] ops
PCI: 00:01.1 [1022/7451] enabled
PCI: 00:02.0 [1022/7450] bus ops
PCI: 00:02.0 [1022/7450] enabled
PCI: 00:02.1 [1022/7451] ops
PCI: 00:02.1 [1022/7451] enabled
PCI: 00:03.0 [1022/7460] enabled
PCI: 00:04.0 [1022/7468] bus ops
PCI: 00:04.0 [1022/7468] enabled
PCI: 00:04.1 [1022/7469] ops
PCI: 00:04.1 [1022/7469] enabled
PCI: 00:04.2 [1022/746a] bus ops
PCI: 00:04.2 [1022/746a] enabled
PCI: 00:04.3 [1022/746b] bus ops
PCI: 00:04.3 [1022/746b] enabled
PCI: 00:04.4, bad id 0x0
PCI: 00:04.6 [1022/746e] ops
PCI: 00:04.6 [1022/746e] enabled
PCI: 00:04.7, bad id 0x0
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
malloc Enter, size 1092, free_mem_ptr 00161554
malloc 00161554
PCI: 01:03.0 [14e4/16a6] enabled
malloc Enter, size 1092, free_mem_ptr 00161998
malloc 00161998
PCI: 01:04.0 [14e4/16a6] enabled
malloc Enter, size 1092, free_mem_ptr 00161ddc
malloc 00161ddc
PCI: 01:05.0 [1095/3114] ops
PCI: 01:05.0 [1095/3114] enabled
PCI: pci_scan_bus returning with max=001
Capability: type 0x07 @ 0xa0
PCI: 01: Conventional PCI
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
Capability: type 0x07 @ 0xa0
PCI: 02: 133MHz PCI-X
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [1022/7464] bus ops
PCI: 03:00.0 [1022/7464] enabled
PCI: 03:00.1 [1022/7464] bus ops
PCI: 03:00.1 [1022/7464] enabled
PCI: 03:06.0 [1002/4752] enabled
scan_static_bus for PCI: 03:00.0
scan_static_bus for PCI: 03:00.0 done
scan_static_bus for PCI: 03:00.1
scan_static_bus for PCI: 03:00.1 done
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
scan_static_bus for PCI: 00:04.0
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 disabled
PNP: 002e.3 enabled
PNP: 002e.4 disabled
PNP: 002e.5 disabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
scan_static_bus for PCI: 00:04.0 done
scan_static_bus for PCI: 00:04.2
scan_static_bus for PCI: 00:04.2 done
scan_static_bus for PCI: 00:04.3
smbus: PCI: 00:04.3[0]->I2C: 01:70 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:50 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:51 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:52 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:53 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:54 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:55 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:56 enabled
smbus: PCI: 00:04.3[0]->I2C: 01:57 enabled
scan_static_bus for PCI: 00:04.3 done
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus returning with max=003
PCI_DOMAIN: 0000 passpw: enabled
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 03:06.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:03.0 read_resources bus 3 link: 0
PCI: 00:03.0 read_resources bus 3 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PCI: 00:04.0 read_resources bus 0 link: 0 done
PCI: 00:04.3 read_resources bus 1 link: 0
I2C: 01:70 missing read_resources
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
I2C: 01:54 missing read_resources
I2C: 01:55 missing read_resources
I2C: 01:56 missing read_resources
I2C: 01:57 missing read_resources
PCI: 00:04.3 read_resources bus 1 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:19.0 read_resources bus 0 link: 0
PCI: 00:19.0 read_resources bus 0 link: 0 done
PCI: 00:19.0 read_resources bus 0 link: 1
PCI: 00:19.0 read_resources bus 0 link: 1 done
PCI: 00:19.0 read_resources bus 0 link: 2
PCI: 00:19.0 read_resources bus 0 link: 2 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:18.0 links 3 child on link 0 PCI: 00:01.0
   PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8
   PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:03.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 01:03.0 links 0 child on link 0 NULL
     PCI: 01:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
     PCI: 01:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
     PCI: 01:04.0 links 0 child on link 0 NULL
     PCI: 01:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
     PCI: 01:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
     PCI: 01:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
     PCI: 01:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
     PCI: 01:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
     PCI: 01:05.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
     PCI: 01:05.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
    PCI: 00:01.1 links 0 child on link 0 NULL
    PCI: 00:01.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
    PCI: 00:02.0 links 1 child on link 0 NULL
    PCI: 00:02.1 links 0 child on link 0 NULL
    PCI: 00:02.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
    PCI: 00:03.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
    PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
     PCI: 03:00.1 links 0 child on link 0 NULL
     PCI: 03:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
     PCI: 03:00.2 links 0 child on link 0 NULL
     PCI: 03:01.0 links 0 child on link 0 NULL
     PCI: 03:06.0 links 0 child on link 0 NULL
     PCI: 03:06.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
     PCI: 03:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 03:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
     PCI: 03:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
    PCI: 00:04.0 links 1 child on link 0 PNP: 002e.0
    PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 378 size 400 align 10 gran 10 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.4 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.6 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62
     PNP: 002e.6 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.a links 0 child on link 0 NULL
     PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:04.1 links 0 child on link 0 NULL
    PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:04.2 links 0 child on link 0 NULL
    PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10
    PCI: 00:04.3 links 1 child on link 0 I2C: 01:70
    PCI: 00:04.3 resource base 0 size 100 align 8 gran 8 limit 10000 flags 100 index 58
     I2C: 01:70 links 4 child on link 0 I2C: 00:2c
      I2C: 00:2c links 0 child on link 0 NULL
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
     I2C: 01:54 links 0 child on link 0 NULL
     I2C: 01:55 links 0 child on link 0 NULL
     I2C: 01:56 links 0 child on link 0 NULL
     I2C: 01:57 links 0 child on link 0 NULL
    PCI: 00:04.5 links 0 child on link 0 NULL
    PCI: 00:04.6 links 0 child on link 0 NULL
    PCI: 00:04.6 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 00:04.6 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 14
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
   PCI: 00:19.0 links 3 child on link 0 NULL
   PCI: 00:19.1 links 0 child on link 0 NULL
   PCI: 00:19.2 links 0 child on link 0 NULL
   PCI: 00:19.3 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 01:05.0 20 *  [0x0 - 0xf] io
PCI: 01:05.0 10 *  [0x10 - 0x17] io
PCI: 01:05.0 18 *  [0x18 - 0x1f] io
PCI: 01:05.0 14 *  [0x20 - 0x23] io
PCI: 01:05.0 1c *  [0x24 - 0x27] io
PCI: 00:01.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 03:06.0 14 *  [0x0 - 0xff] io
PCI: 00:03.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:03.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:04.3 58 *  [0x2000 - 0x20ff] io
PCI: 00:04.6 10 *  [0x2400 - 0x24ff] io
PCI: 00:04.6 14 *  [0x2800 - 0x287f] io
PCI: 00:04.2 10 *  [0x2880 - 0x289f] io
PCI: 00:04.1 20 *  [0x28a0 - 0x28af] io
PCI: 00:18.0 compute_resources_io: base: 28b0 size: 3000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 00 *  [0x0 - 0x2fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 30 *  [0x0 - 0x7ffff] mem
PCI: 01:03.0 10 *  [0x80000 - 0x8ffff] mem
PCI: 01:03.0 30 *  [0x90000 - 0x9ffff] mem
PCI: 01:04.0 10 *  [0xa0000 - 0xaffff] mem
PCI: 01:04.0 30 *  [0xb0000 - 0xbffff] mem
PCI: 01:05.0 24 *  [0xc0000 - 0xc03ff] mem
PCI: 00:01.0 compute_resources_mem: base: c0400 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:06.0 10 *  [0x0 - 0xffffff] mem
PCI: 03:06.0 30 *  [0x1000000 - 0x101ffff] mem
PCI: 03:00.0 10 *  [0x1020000 - 0x1020fff] mem
PCI: 03:00.1 10 *  [0x1021000 - 0x1021fff] mem
PCI: 03:06.0 18 *  [0x1022000 - 0x1022fff] mem
PCI: 00:03.0 compute_resources_mem: base: 1023000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:03.0 20 *  [0x0 - 0x10fffff] mem
PCI: 00:01.0 20 *  [0x1100000 - 0x11fffff] mem
PCI: 00:01.1 10 *  [0x1200000 - 0x1200fff] mem
PCI: 00:02.1 10 *  [0x1201000 - 0x1201fff] mem
PCI: 00:18.0 compute_resources_mem: base: 1202000 size: 1300000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
PCI: 00:18.0 01 *  [0x4000000 - 0x52fffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 5300000 size: 5300000 align: 26 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:03.0
constrain_resources: PCI: 01:04.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:02.1
constrain_resources: PCI: 00:03.0
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 03:00.1
constrain_resources: PCI: 03:06.0
constrain_resources: PCI: 00:04.0
constrain_resources: PNP: 002e.3
constrain_resources: PNP: 002e.6
constrain_resources: PCI: 00:04.1
constrain_resources: PCI: 00:04.2
constrain_resources: PCI: 00:04.3
constrain_resources: I2C: 01:70
constrain_resources: I2C: 00:2c
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: I2C: 01:52
constrain_resources: I2C: 01:53
constrain_resources: I2C: 01:54
constrain_resources: I2C: 01:55
constrain_resources: I2C: 01:56
constrain_resources: I2C: 01:57
constrain_resources: PCI: 00:04.6
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:19.0
constrain_resources: PCI: 00:19.1
constrain_resources: PCI: 00:19.2
constrain_resources: PCI: 00:19.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
	lim->base 000c0000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 00 *  [0x1000 - 0x3fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:03.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:04.3 58 *  [0x3000 - 0x30ff] io
Assigned: PCI: 00:04.6 10 *  [0x3400 - 0x34ff] io
Assigned: PCI: 00:04.6 14 *  [0x3800 - 0x387f] io
Assigned: PCI: 00:04.2 10 *  [0x3880 - 0x389f] io
Assigned: PCI: 00:04.1 20 *  [0x38a0 - 0x38af] io
PCI: 00:18.0 allocate_resources_io: next_base: 38b0 size: 3000 align: 12 gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 20 *  [0x1000 - 0x100f] io
Assigned: PCI: 01:05.0 10 *  [0x1010 - 0x1017] io
Assigned: PCI: 01:05.0 18 *  [0x1018 - 0x101f] io
Assigned: PCI: 01:05.0 14 *  [0x1020 - 0x1023] io
Assigned: PCI: 01:05.0 1c *  [0x1024 - 0x1027] io
PCI: 00:01.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done
PCI: 00:03.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 03:06.0 14 *  [0x2000 - 0x20ff] io
PCI: 00:03.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:5300000 align:26 gran:0 limit:febfffff
Assigned: PCI: 00:18.3 94 *  [0xf8000000 - 0xfbffffff] mem
Assigned: PCI: 00:18.0 01 *  [0xfc000000 - 0xfd2fffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fd300000 size: 5300000 align: 26 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:1300000 align:24 gran:20 limit:febfffff
Assigned: PCI: 00:03.0 20 *  [0xfc000000 - 0xfd0fffff] mem
Assigned: PCI: 00:01.0 20 *  [0xfd100000 - 0xfd1fffff] mem
Assigned: PCI: 00:01.1 10 *  [0xfd200000 - 0xfd200fff] mem
Assigned: PCI: 00:02.1 10 *  [0xfd201000 - 0xfd201fff] mem
PCI: 00:18.0 allocate_resources_mem: next_base: fd202000 size: 1300000 align: 24 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:fd100000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:05.0 30 *  [0xfd100000 - 0xfd17ffff] mem
Assigned: PCI: 01:03.0 10 *  [0xfd180000 - 0xfd18ffff] mem
Assigned: PCI: 01:03.0 30 *  [0xfd190000 - 0xfd19ffff] mem
Assigned: PCI: 01:04.0 10 *  [0xfd1a0000 - 0xfd1affff] mem
Assigned: PCI: 01:04.0 30 *  [0xfd1b0000 - 0xfd1bffff] mem
Assigned: PCI: 01:05.0 24 *  [0xfd1c0000 - 0xfd1c03ff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: fd1c0400 size: 100000 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_mem: base:fc000000 size:1100000 align:24 gran:20 limit:febfffff
Assigned: PCI: 03:06.0 10 *  [0xfc000000 - 0xfcffffff] mem
Assigned: PCI: 03:06.0 30 *  [0xfd000000 - 0xfd01ffff] mem
Assigned: PCI: 03:00.0 10 *  [0xfd020000 - 0xfd020fff] mem
Assigned: PCI: 03:00.1 10 *  [0xfd021000 - 0xfd021fff] mem
Assigned: PCI: 03:06.0 18 *  [0xfd022000 - 0xfd022fff] mem
PCI: 00:03.0 allocate_resources_mem: next_base: fd023000 size: 1100000 align: 24 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=003e0000, basek=00000300, limitk=00200000
1: mmio_basek=003e0000, basek=003e0000, limitk=00400000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fd2fffff] size 0x01300000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00fd100000 - 0x00fd1fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:03.0 10 <- [0x00fd180000 - 0x00fd18ffff] size 0x00010000 gran 0x10 mem64
PCI: 01:03.0 30 <- [0x00fd190000 - 0x00fd19ffff] size 0x00010000 gran 0x10 romem
PCI: 01:04.0 10 <- [0x00fd1a0000 - 0x00fd1affff] size 0x00010000 gran 0x10 mem64
PCI: 01:04.0 30 <- [0x00fd1b0000 - 0x00fd1bffff] size 0x00010000 gran 0x10 romem
PCI: 01:05.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io
PCI: 01:05.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io
PCI: 01:05.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io
PCI: 01:05.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io
PCI: 01:05.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io
PCI: 01:05.0 24 <- [0x00fd1c0000 - 0x00fd1c03ff] size 0x00000400 gran 0x0a mem
PCI: 01:05.0 30 <- [0x00fd100000 - 0x00fd17ffff] size 0x00080000 gran 0x13 romem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:01.1 10 <- [0x00fd200000 - 0x00fd200fff] size 0x00001000 gran 0x0c mem64
PCI: 00:02.1 10 <- [0x00fd201000 - 0x00fd201fff] size 0x00001000 gran 0x0c mem64
PCI: 00:03.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:03.0 20 <- [0x00fc000000 - 0x00fd0fffff] size 0x01100000 gran 0x14 bus 03 mem
PCI: 00:03.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00fd020000 - 0x00fd020fff] size 0x00001000 gran 0x0c mem
PCI: 03:00.1 10 <- [0x00fd021000 - 0x00fd021fff] size 0x00001000 gran 0x0c mem
PCI: 03:06.0 10 <- [0x00fc000000 - 0x00fcffffff] size 0x01000000 gran 0x18 mem
PCI: 03:06.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 03:06.0 18 <- [0x00fd022000 - 0x00fd022fff] size 0x00001000 gran 0x0c mem
PCI: 03:06.0 30 <- [0x00fd000000 - 0x00fd01ffff] size 0x00020000 gran 0x11 romem
PCI: 00:03.0 assign_resources, bus 3 link: 0
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.6 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io
PNP: 002e.6 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io
PNP: 002e.6 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x00000038a0 - 0x00000038af] size 0x00000010 gran 0x04 io
PCI: 00:04.2 10 <- [0x0000003880 - 0x000000389f] size 0x00000020 gran 0x05 io
PCI: 00:04.3 58 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io
PCI: 00:04.3 assign_resources, bus 1 link: 0
PCI: 00:04.3 assign_resources, bus 1 link: 0
PCI: 00:04.6 10 <- [0x0000003400 - 0x00000034ff] size 0x00000100 gran 0x08 io
PCI: 00:04.6 14 <- [0x0000003800 - 0x000000387f] size 0x00000080 gran 0x07 io
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base f8000000 size 5300000 align 26 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 80000000 size 78000000 align 0 gran 0 limit 0 flags e0004200 index 31
   PCI: 00:18.0 links 3 child on link 0 PCI: 00:01.0
   PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 1c0
   PCI: 00:18.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 40081200 index 2
   PCI: 00:18.0 resource base fc000000 size 1300000 align 24 gran 20 limit febfffff flags 60080200 index 1b8
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1b0
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:03.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:01.0 resource base fd100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 01:03.0 links 0 child on link 0 NULL
     PCI: 01:03.0 resource base fd180000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10
     PCI: 01:03.0 resource base fd190000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
     PCI: 01:04.0 links 0 child on link 0 NULL
     PCI: 01:04.0 resource base fd1a0000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10
     PCI: 01:04.0 resource base fd1b0000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
     PCI: 01:05.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
     PCI: 01:05.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
     PCI: 01:05.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
     PCI: 01:05.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
     PCI: 01:05.0 resource base fd1c0000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
     PCI: 01:05.0 resource base fd100000 size 80000 align 19 gran 19 limit febfffff flags 60002200 index 30
    PCI: 00:01.1 links 0 child on link 0 NULL
    PCI: 00:01.1 resource base fd200000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10
    PCI: 00:02.0 links 1 child on link 0 NULL
    PCI: 00:02.1 links 0 child on link 0 NULL
    PCI: 00:02.1 resource base fd201000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10
    PCI: 00:03.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:03.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
    PCI: 00:03.0 resource base fc000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base fd020000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
     PCI: 03:00.1 links 0 child on link 0 NULL
     PCI: 03:00.1 resource base fd021000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
     PCI: 03:00.2 links 0 child on link 0 NULL
     PCI: 03:01.0 links 0 child on link 0 NULL
     PCI: 03:06.0 links 0 child on link 0 NULL
     PCI: 03:06.0 resource base fc000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
     PCI: 03:06.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
     PCI: 03:06.0 resource base fd022000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 18
     PCI: 03:06.0 resource base fd000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
    PCI: 00:04.0 links 1 child on link 0 PNP: 002e.0
    PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 378 size 400 align 10 gran 10 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.4 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.6 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62
     PNP: 002e.6 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.a links 0 child on link 0 NULL
     PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:04.1 links 0 child on link 0 NULL
    PCI: 00:04.1 resource base 38a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:04.2 links 0 child on link 0 NULL
    PCI: 00:04.2 resource base 3880 size 20 align 5 gran 5 limit ffff flags 60000100 index 10
    PCI: 00:04.3 links 1 child on link 0 I2C: 01:70
    PCI: 00:04.3 resource base 3000 size 100 align 8 gran 8 limit ffff flags 60000100 index 58
     I2C: 01:70 links 4 child on link 0 I2C: 00:2c
      I2C: 00:2c links 0 child on link 0 NULL
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
     I2C: 01:54 links 0 child on link 0 NULL
     I2C: 01:55 links 0 child on link 0 NULL
     I2C: 01:56 links 0 child on link 0 NULL
     I2C: 01:57 links 0 child on link 0 NULL
    PCI: 00:04.5 links 0 child on link 0 NULL
    PCI: 00:04.6 links 0 child on link 0 NULL
    PCI: 00:04.6 resource base 3400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 00:04.6 resource base 3800 size 80 align 7 gran 7 limit ffff flags 60000100 index 14
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94
   PCI: 00:19.0 links 3 child on link 0 NULL
   PCI: 00:19.1 links 0 child on link 0 NULL
   PCI: 00:19.2 links 0 child on link 0 NULL
   PCI: 00:19.3 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 07
PCI: 01:03.0 cmd <- 02
PCI: 01:04.0 cmd <- 02
PCI: 01:05.0 cmd <- 03
PCI: 00:01.1 subsystem <- 161f/3016
PCI: 00:01.1 cmd <- 06
PCI: 00:02.1 subsystem <- 161f/3016
PCI: 00:02.1 cmd <- 06
PCI: 00:03.0 bridge ctrl <- 000b
PCI: 00:03.0 cmd <- 07
PCI: 03:00.0 subsystem <- 161f/3016
PCI: 03:00.0 cmd <- 02
PCI: 03:00.1 subsystem <- 161f/3016
PCI: 03:00.1 cmd <- 02
PCI: 03:06.0 subsystem <- 161f/3016
PCI: 03:06.0 cmd <- 83
PCI: 00:04.0 subsystem <- 161f/3016
PCI: 00:04.0 cmd <- 0f
PCI: 00:04.1 subsystem <- 161f/3016
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 subsystem <- 161f/3016
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 subsystem <- 161f/3016
PCI: 00:04.3 cmd <- 01
PCI: 00:04.6 subsystem <- 161f/3016
PCI: 00:04.6 cmd <- 01
PCI: 00:18.1 subsystem <- 161f/3016
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 161f/3016
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:19.0 cmd <- 00
PCI: 00:19.1 cmd <- 00
PCI: 00:19.2 cmd <- 00
PCI: 00:19.3 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x0000c000, offset=0x00100000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device f51
CPU: family 0f, model 05, stepping 01
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range:  512MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 3, base: 3584MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 4, base: 3840MB, range:  128MB, type WB
ADDRESS_MASK_HIGH=0xff
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model AMD Opteron(tm) Processor 242
Setting up local apic... apic_id: 0x00 done.
Clearing memory 2048K - 2097152K: ------------------------------- done
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device f51
CPU: family 0f, model 05, stepping 01
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base: 3072MB, range:  512MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 3, base: 3584MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 4, base: 3840MB, range:  128MB, type WB
ADDRESS_MASK_HIGH=0xff
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model AMD Opteron(tm) Processor 242
Setting up local apic... apic_id: 0x01 done.
Clearing memory 2097152K - 4194304K: -------------------------------- done
CPU #1 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:01.0 init
PCI: 00:03.0 init
PCI: 03:06.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
In cbfs, rom address for PCI: 03:06.0 = fff93378
PCI Expansion ROM, signature 0xaa55, INIT size 0x9000, data ptr 0x017c
PCI ROM Image, Vendor 1002, Device 4752,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff93378 to 0xc0000, 0x9000 bytes
Real mode stub @00000600: 609 bytes
Calling Option ROM...
oprom: INT# 0x1a
oprom: eax: 0000b109 ebx: 00000000 ecx: 00000000 edx: 00000000
oprom: ebp: 0015ff00 esp: 00000fd6 edi: 0000002e esi: 00000000
oprom:  ip: 02b6      cs: c000   flags: 00000046
0xb109: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b10d ebx: 00000000 ecx: 80081002 edx: 00000000
oprom: ebp: 0015ff00 esp: 00000fd6 edi: 0000004c esi: 00000000
oprom:  ip: 02c8      cs: c000   flags: 00000046
0xb10d: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b109 ebx: 00000000 ecx: 80081002 edx: 00000000
oprom: ebp: 0015ff00 esp: 00000fd6 edi: 00000014 esi: 00000000
oprom:  ip: 0322      cs: c000   flags: 00000046
0xb109: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b10a ebx: 00000000 ecx: 8008efff edx: 00000000
oprom: ebp: 0015ff00 esp: 00000fd6 edi: 00000018 esi: 00000000
oprom:  ip: 0347      cs: c000   flags: 00000006
0xb10a: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b108 ebx: 00000000 ecx: 00000084 edx: 0000b108
oprom: ebp: 00150fa4 esp: 00000f96 edi: 00000004 esi: 000001c9
oprom:  ip: 84c9      cs: c000   flags: 00000046
0xb108: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b10b ebx: 00000000 ecx: 00000084 edx: 0000b10b
oprom: ebp: 00150fa4 esp: 00000f9a edi: 00000004 esi: 000001ca
oprom:  ip: 83fb      cs: c000   flags: 00000046
0xb10b: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x1a
oprom: eax: 0000b10a ebx: 00000000 ecx: 00005884 edx: 0000b10a
oprom: ebp: 00150fa4 esp: 00000f96 edi: 00000003 esi: 00000273
oprom:  ip: 84c9      cs: c000   flags: 00000016
0xb10a: BAD DEVICE bus 0 devfn 0x0
int1a call returned error.
oprom: INT# 0x42
oprom: eax: 00000007 ebx: 00001004 ecx: 00000000 edx: 000003c2
oprom: ebp: 00150000 esp: 00000fdc edi: 0000efff esi: 00000000
oprom:  ip: 4302      cs: c000   flags: 00000006
Unsupported software interrupt #0x42
int42 call returned error.
... Option ROM returned.
PCI: 00:04.0 init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 00
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
RTC Init
Invalid CMOS LB checksum
enabling HPET @0xfed00000
PNP: 002e.3 init
PNP: 002e.6 init
Keyboard init...
Keyboard controller output buffer result timeout
PCI: 00:04.1 init
IDE1 IDE0 PCI: 00:04.3 init
set power on after power fail
PCI: 00:18.1 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:18.2 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:19.0 init
PCI: 00:19.1 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:19.2 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:19.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:03.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci14e4,16a6.rom
On card, rom address for PCI: 01:03.0 = fd190000
PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff
Incorrect Expansion ROM Header Signature ffff
PCI: 01:04.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
CBFS: follow chain: fff8ab80 + 38 + 877a + align -> fff93340
Check pci1002,4752.rom
CBFS: follow chain: fff93340 + 38 + 9000 + align -> fff9c380
Check 
CBFS: follow chain: fff9c380 + 28 + 53c38 + align -> ffff0000
CBFS:  Could not find file pci14e4,16a6.rom
On card, rom address for PCI: 01:04.0 = fd1b0000
PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff
Incorrect Expansion ROM Header Signature ffff
PCI: 01:05.0 init
SIL3114 set to IDE compatible mode
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 5 resources
PCI: 00:18.0: enabled 1, 4 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 00:01.1: enabled 1, 1 resources
PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:02.1: enabled 1, 1 resources
PCI: 00:03.0: enabled 1, 3 resources
PCI: 03:00.0: enabled 1, 1 resources
PCI: 03:00.1: enabled 1, 1 resources
PCI: 03:00.2: enabled 0, 0 resources
PCI: 03:01.0: enabled 0, 0 resources
PCI: 03:06.0: enabled 1, 4 resources
PCI: 00:04.0: enabled 1, 3 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 3 resources
PNP: 002e.2: enabled 0, 4 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.4: enabled 0, 2 resources
PNP: 002e.5: enabled 0, 1 resources
PNP: 002e.6: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 2 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 2 resources
PNP: 002e.a: enabled 0, 2 resources
PCI: 00:04.1: enabled 1, 1 resources
PCI: 00:04.2: enabled 1, 1 resources
PCI: 00:04.3: enabled 1, 1 resources
I2C: 01:70: enabled 1, 0 resources
I2C: 00:2c: enabled 1, 0 resources
I2C: 01:50: enabled 1, 0 resources
I2C: 01:51: enabled 1, 0 resources
I2C: 01:52: enabled 1, 0 resources
I2C: 01:53: enabled 1, 0 resources
I2C: 01:54: enabled 1, 0 resources
I2C: 01:55: enabled 1, 0 resources
I2C: 01:56: enabled 1, 0 resources
I2C: 01:57: enabled 1, 0 resources
PCI: 00:04.5: enabled 0, 0 resources
PCI: 00:04.6: enabled 1, 2 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
PCI: 00:19.0: enabled 1, 0 resources
PCI: 00:19.1: enabled 1, 0 resources
PCI: 00:19.2: enabled 1, 0 resources
PCI: 00:19.3: enabled 1, 0 resources
APIC: 01: enabled 1, 0 resources
PCI: 01:03.0: enabled 1, 2 resources
PCI: 01:04.0: enabled 1, 2 resources
PCI: 01:05.0: enabled 1, 7 resources
Initializing CBMEM area to 0x7fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 7fff0200...ok
High Tables Base is 7fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x7fff0400... done.
PIRQ table: 176 bytes.
Looking for bad PCIX MHz input
Looking for bad Hot Swap Enable
OK 133MHz & Hot Swap is off
Wrote the mp table end at: 000f0410 - 000f060c
Adding CBMEM entry as no. 3
Looking for bad PCIX MHz input
Looking for bad Hot Swap Enable
OK 133MHz & Hot Swap is off
Wrote the mp table end at: 7fff1410 - 7fff160c
MP table: 524 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 5bdf
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x7fff2400
rom_table_end = 0x7fff2400
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x7fff2400 to 0x80000000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000007ffeffff: RAM
 3. 000000007fff0000-000000007fffffff: CONFIGURATION TABLES
 4. 0000000080000000-00000000f7ffffff: RAM
Wrote coreboot table at: 7fff2400 - 7fff2cd8  checksum 827d
coreboot table: 2264 bytes.
 0. FREE SPACE 7fff4400 0000bc00
 1. GDT        7fff0200 00000200
 2. IRQ TABLE  7fff0400 00001000
 3. SMP TABLE  7fff1400 00001000
 4. COREBOOT   7fff2400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + ab2b + align -> fff8ab80
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff8abb8
  parameter section (skipped)
Loading segment from rom address 0xfff8abd4
  data (compression=1)
malloc Enter, size 36, free_mem_ptr 00162220
malloc 00162220
  New segment dstaddr 0x100000 memsize 0x136270 srcaddr 0xfff8ac58 filesize 0x86ad
  (cleaned up) New segment addr 0x100000 size 0x136270 offset 0xfff8ac58 filesize 0x86ad
Loading segment from rom address 0xfff8abf0
  data (compression=1)
malloc Enter, size 36, free_mem_ptr 00162244
malloc 00162244
  New segment dstaddr 0x236270 memsize 0x48 srcaddr 0xfff93305 filesize 0x2d
  (cleaned up) New segment addr 0x236270 size 0x48 offset 0xfff93305 filesize 0x2d
Loading segment from rom address 0xfff8ac0c
  Entry Point 0x00100000
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000136270 filesz: 0x00000000000086ad
lb: [0x0000000000100000, 0x0000000000164000)
segment: [0x0000000000100000, 0x00000000001086ad, 0x0000000000236270)
 bounce: [0x00000000f7e65d90, 0x00000000f7e6e43d, 0x00000000f7f9c000)
Post relocation: addr: 0x00000000f7e65d90 memsz: 0x0000000000136270 filesz: 0x00000000000086ad
using LZMA
[ 0x00000000f7e65d90, 00000000f7e79054, 0x00000000f7f9c000) <- 00000000fff8ac58
Clearing Segment: addr: 0x00000000f7e79054 memsz: 0x0000000000122fac
dest f7e65d90, end f7f9c000, bouncebuffer f7e65d90
move suffix around: from f7ec9d90, to 164000, amount: d2270
Loading Segment: addr: 0x0000000000236270 memsz: 0x0000000000000048 filesz: 0x000000000000002d
lb: [0x0000000000100000, 0x0000000000164000)
Post relocation: addr: 0x0000000000236270 memsz: 0x0000000000000048 filesz: 0x000000000000002d
using LZMA
[ 0x0000000000236270, 00000000002362b8, 0x00000000002362b8) <- 00000000fff93305
dest 00236270, end 002362b8, bouncebuffer f7e65d90
Loaded segments
Jumping to boot code at 100000
entry    = 0x00100000
lb_start = 0x00100000
lb_size  = 0x00064000
adjust   = 0xf7e9c000
buffer   = 0xf7e65d90
     elf_boot_notes = 0x00114c30
adjusted_boot_notes = 0xf7fb0c30
FILO version 0.6.0 (jboonen@phenomII) Wed May 19 23:00:58 CEST 2010
00:00.1 7464:1022.1 OHCI controller
Not supported.
00:00.0 7464:1022.0 OHCI controller
Not supported.
Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out
boot: hda1:/vmlinuz root=/dev/hda3 console=tty0 console=ttyS0,115200
IDE time out
reset failed, but slave may exist
hda: LBA48 80GB: SAMSUNG HD080HJ                         
Found Linux version 2.6.31.12-0.2-desktop (geeko@buildhost) #1 SMP PREEMPT 2010-03-16 21:25:39 +0100 bzImage.
Loading kernel... ok
Jumping to entry point...
[    0.000000] Linux version 2.6.31.12-0.2-desktop (geeko@buildhost) (gcc version 4.4.1 [gcc-4_4-branch revision 150839] (SUSE Linux) ) #1 SMP PREEMPT 2010-03-16 21:25:39 +0100
[    0.000000] Command line: root=/dev/hda3 console=tty0 console=ttyS0,115200
[    0.000000] KERNEL supported cpus:
[    0.000000]   Intel GenuineIntel
[    0.000000]   AMD AuthenticAMD
[    0.000000]   Centaur CentaurHauls
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 0000000000001000 type 16
[    0.000000]  BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
[    0.000000]  BIOS-e820: 00000000000c0000 - 000000007fff0000 (usable)
[    0.000000]  BIOS-e820: 000000007fff0000 - 0000000080000000 type 16
[    0.000000]  BIOS-e820: 0000000080000000 - 00000000f8000000 (usable)
[    0.000000] DMI not present or invalid.
[    0.000000] last_pfn = 0xf8000 max_arch_pfn = 0x400000000
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] Scanning 2 areas for low memory corruption
[    0.000000] modified physical RAM map:
[    0.000000]  modified: 0000000000000000 - 0000000000001000 type 16
[    0.000000]  modified: 0000000000001000 - 0000000000006000 (reserved)
[    0.000000]  modified: 0000000000006000 - 0000000000008000 (usable)
[    0.000000]  modified: 0000000000008000 - 0000000000010000 (reserved)
[    0.000000]  modified: 0000000000010000 - 00000000000a0000 (usable)
[    0.000000]  modified: 00000000000c0000 - 000000007fff0000 (usable)
[    0.000000]  modified: 000000007fff0000 - 0000000080000000 type 16
[    0.000000]  modified: 0000000080000000 - 00000000f8000000 (usable)
[    0.000000] init_memory_mapping: 0000000000000000-00000000f8000000
[    0.000000] ACPI Error: A valid RSDP was not found 20090521 tbxfroot-219
[    0.000000] Scanning NUMA topology in Northbridge 24
[    0.000000] Number of nodes 2
[    0.000000] Node 0 MemBase 0000000000000000 Limit 0000000080000000
[    0.000000] Node 1 MemBase 0000000080000000 Limit 00000000f8000000
[    0.000000] Using node hash shift of 31
[    0.000000] found SMP MP-table at [ffff8800000f0400] f0400
[    0.000000] Intel MultiProcessor Specification v1.4
[    0.000000] MPTABLE: OEM ID: COREBOOT
[    0.000000] MPTABLE: Product ID: HDAMA       
[    0.000000] MPTABLE: APIC at: 0xFEE00000
[    0.000000] Bootmem setup node 0 0000000000000000-0000000080000000
[    0.000000]   NODE_DATA [0000000000013000 - 000000000002afff]
[    0.000000]   bootmap [000000000002b000 -  000000000003afff] pages 10
[    0.000000] (5 early reservations) ==> bootmem [0000000000 - 0080000000]
[    0.000000]   #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
[    0.000000]   #1 [0000006000 - 0000008000]       TRAMPOLINE ==> [0000006000 - 0000008000]
[    0.000000]   #2 [0001000000 - 0001c4bf70]    TEXT DATA BSS ==> [0001000000 - 0001c4bf70]
[    0.000000]   #3 [00000f6000 - 0000100000]    BIOS reserved ==> [00000f6000 - 0000100000]
[    0.000000]   #4 [0000010000 - 0000013000]          PGTABLE ==> [0000010000 - 0000013000]
[    0.000000] Bootmem setup node 1 0000000080000000-00000000f8000000
[    0.000000]   NODE_DATA [0000000080000000 - 0000000080017fff]
[    0.000000]   bootmap [0000000080018000 -  0000000080026fff] pages f
[    0.000000] (5 early reservations) ==> bootmem [0080000000 - 00f8000000]
[    0.000000]   #0 [0000000000 - 0000001000]   BIOS data page
[    0.000000]   #1 [0000006000 - 0000008000]       TRAMPOLINE
[    0.000000]   #2 [0001000000 - 0001c4bf70]    TEXT DATA BSS
[    0.000000]   #3 [00000f6000 - 0000100000]    BIOS reserved
[    0.000000]   #4 [0000010000 - 0000013000]          PGTABLE
[    0.000000] found SMP MP-table at [ffff8800000f0400] f0400
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000006 -> 0x00001000
[    0.000000]   DMA32    0x00001000 -> 0x00100000
[    0.000000]   Normal   0x00100000 -> 0x00100000
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[4] active PFN ranges
[    0.000000]     0: 0x00000006 -> 0x00000008
[    0.000000]     0: 0x00000010 -> 0x000000a0
[    0.000000]     0: 0x000000c0 -> 0x0007fff0
[    0.000000]     1: 0x00080000 -> 0x000f8000
[    0.000000] Intel MultiProcessor Specification v1.4
[    0.000000] MPTABLE: OEM ID: COREBOOT
[    0.000000] MPTABLE: Product ID: HDAMA       
[    0.000000] MPTABLE: APIC at: 0xFEE00000
[    0.000000] Processor #0 (Bootup-CPU)
[    0.000000] Processor #1
[    0.000000] I/O APIC #2 Version 17 at 0xFEC00000.
[    0.000000] I/O APIC #3 Version 17 at 0xFD200000.
[    0.000000] I/O APIC #4 Version 17 at 0xFD201000.
[    0.000000] Processors: 2
[    0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
[    0.000000] PM: Registered nosave memory: 0000000000001000 - 0000000000006000
[    0.000000] PM: Registered nosave memory: 0000000000008000 - 0000000000010000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000c0000
[    0.000000] PM: Registered nosave memory: 000000007fff0000 - 0000000080000000
[    0.000000] Allocating PCI resources starting at f8000000 (gap: f8000000:8000000)
[    0.000000] NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:2 nr_node_ids:2
[    0.000000] PERCPU: Remapped at ffffc90000000000 with large pages, static data 82784 bytes
[    0.000000] Built 2 zonelists in Node order, mobility grouping on.  Total pages: 1001842
[    0.000000] Policy zone: DMA32
[    0.000000] Kernel command line: root=/dev/hda3 console=tty0 console=ttyS0,115200
[    0.000000] PID hash table entries: 4096 (order: 12, 32768 bytes)
[    0.000000] Initializing CPU#0
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Node 0: aperture @ f8000000 size 64 MB
[    0.000000] Node 1: aperture @ f8000000 size 64 MB
[    0.000000] Memory: 3992180k/4063232k available (5500k kernel code, 248k absent, 70804k reserved, 4470k data, 980k init)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS:4352 nr_irqs:512
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 1603.601 MHz processor.
[    0.000999] Console: colour VGA+ 80x25
[    0.000999] console [tty0] enabled
[    0.000999] console [ttyS0] enabled
[    0.001013] Calibrating delay loop (skipped), value calculated using timer frequency.. 3207.20 BogoMIPS (lpj=1603601)
[    0.010062] kdb version 4.4 by Keith Owens, Scott Lurndal. Copyright SGI, All Rights Reserved
kdb_cmd[0]: defcmd archkdb "" "First line arch debugging"
kdb_cmd[7]: defcmd archkdbcpu "" "archkdb with only tasks on cpus"
kdb_cmd[14]: defcmd archkdbshort "" "archkdb with less detailed backtrace"
kdb_cmd[21]: defcmd archkdbcommon "" "Common arch debugging"
[    0.015229] Security Framework initialized
[    0.016033] AppArmor: AppArmor initialized
[    0.018019] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.023768] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.025854] Mount-cache hash table entries: 256
[    0.026340] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.027001] CPU: L2 Cache: 1024K (64 bytes/line)
[    0.028001] CPU 0/0x0 -> Node 0
[    0.029022] mce: CPU supports 5 MCE banks
[    0.030013] Performance Counters: AMD PMU driver.
[    0.032001] ... version:                 0
[    0.032998] ... bit width:               48
[    0.033998] ... generic counters:        4
[    0.034998] ... value mask:              0000ffffffffffff
[    0.035998] ... max period:              00007fffffffffff
[    0.036997] ... fixed-purpose counters:  0
[    0.037998] ... counter mask:            000000000000000f
[    0.040386] Setting APIC routing to flat
[    0.041526] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
[    0.052032] CPU0: AMD Opteron(tm) Processor 242 stepping 01
[    0.160022] Booting processor 1 APIC 0x1 ip 0x6000
[    0.000999] Initializing CPU#1
[    0.000999] Calibrating delay using timer specific routine.. 3206.72 BogoMIPS (lpj=1603364)
[    0.000999] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.000999] CPU: L2 Cache: 1024K (64 bytes/line)
[    0.000999] CPU 1/0x1 -> Node 1
[    0.000999] mce: CPU supports 5 MCE banks
[    0.000999] x86 PAT enabled: cpu 1, old 0x7040600070406, new 0x7010600070106
[    0.232863] CPU1: AMD Opteron(tm) Processor 242 stepping 01
[    0.235028] Brought up 2 CPUs
[    0.237971] Total of 2 processors activated (6413.93 BogoMIPS).
[    0.245091] devtmpfs: initialized
[    0.253998] Booting paravirtualized kernel on bare hardware
[    0.260202] regulator: core version 0.5
[    0.263997] Time: 23:54:32  Date: 05/13/10
[    0.269090] NET: Registered protocol family 16
[    0.273259] TOM: 00000000f8000000 aka 3968M
[    0.277977] TOM2: 0000000000000000 aka 0M
[    0.282968] PCI: Using configuration type 1 for base access
[    0.290131] bio: create slab <bio-0> at 0
[    0.295057] ACPI: Interpreter disabled.
[    0.299308] SCSI subsystem initialized
[    0.303006] usbcore: registered new interface driver usbfs
[    0.308981] usbcore: registered new interface driver hub
[    0.314978] usbcore: registered new device driver usb
[    0.320094] PCI: Probing PCI hardware
[    0.324483] pci 0000:01:03.0: PME# supported from D3hot D3cold
[    0.331006] pci 0000:01:03.0: PME# disabled
[    0.335088] pci 0000:01:04.0: PME# supported from D3hot D3cold
[    0.341005] pci 0000:01:04.0: PME# disabled
[    0.346888] PCI: Discovered primary peer bus 04 [IRQ]
[    0.357612] AppArmor: AppArmor Filesystem Enabled
[    0.363006] pnp: PnP ACPI: disabled
[    0.367376] pci 0000:00:01.0: PCI bridge, secondary bus 0000:01
[    0.373005] pci 0000:00:01.0:   IO window: 0x1000-0x1fff
[    0.379006] pci 0000:00:01.0:   MEM window: 0xfd100000-0xfd1fffff
[    0.385005] pci 0000:00:01.0:   PREFETCH window: disabled
[    0.390005] pci 0000:00:02.0: PCI bridge, secondary bus 0000:02
[    0.397003] pci 0000:00:02.0:   IO window: disabled
[    0.402004] pci 0000:00:02.0:   MEM window: disabled
[    0.407004] pci 0000:00:02.0:   PREFETCH window: disabled
[    0.412007] pci 0000:00:03.0: PCI bridge, secondary bus 0000:03
[    0.418004] pci 0000:00:03.0:   IO window: 0x2000-0x2fff
[    0.424007] pci 0000:00:03.0:   MEM window: 0xfc000000-0xfd0fffff
[    0.430005] pci 0000:00:03.0:   PREFETCH window: disabled
[    0.436250] NET: Registered protocol family 2
[    0.441369] IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.451756] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
[    0.467260] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.475851] TCP: Hash tables configured (established 524288 bind 65536)
[    0.482006] TCP reno registered
[    0.486303] NET: Registered protocol family 1
[    0.490314] platform rtc_cmos: registered platform RTC device (no PNP device found)
[    0.499637] Scanning for low memory corruption every 60 seconds
[    0.505308] audit: initializing netlink socket (disabled)
[    0.511022] type=2000 audit(1273794871.511:1): initialized
[    0.522053] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    0.529041] VFS: Disk quotas dquot_6.5.2
[    0.533084] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.539392] msgmni has been set to 1949
[    0.544211] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    0.552005] io scheduler noop registered
[    0.556003] io scheduler anticipatory registered
[    0.561003] io scheduler deadline registered
[    0.565047] io scheduler cfq registered (default)
[    0.570154] pci 0000:00:01.0: MSI quirk detected; subordinate MSI disabled
[    0.577011] disabled boot interrupts on PCI device 0x1022:0x7450
[    0.583005] pci 0000:00:01.0: AMD8131 rev 12 detected; disabling PCI-X MMRBC
[    0.591011] pci 0000:00:02.0: MSI quirk detected; subordinate MSI disabled
[    0.598005] disabled boot interrupts on PCI device 0x1022:0x7450
[    0.604005] pci 0000:00:02.0: AMD8131 rev 12 detected; disabling PCI-X MMRBC
[    0.611020] boot interrupts on PCI device 0x1022:0x746b already disabled
[    0.618260] pci-stub: invalid id string ""
[    0.624992] Non-volatile memory driver v1.3
[    0.630006] Linux agpgart interface v0.103
[    0.634008] Serial: 8250/16550 driver, 8 ports, IRQ sharing disabled
[    0.641126] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.647399] serial 0000:00:04.6: can't find IRQ for PCI INT B; probably buggy MP table
[    0.648229] Fixed MDIO Bus: probed
[    0.652013] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.659035] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    0.665025] ohci_hcd 0000:03:00.0: can't find IRQ for PCI INT D; probably buggy MP table
[    0.666010] ohci_hcd 0000:03:00.0: Found HC with no IRQ.  Check BIOS/PCI 0000:03:00.0 setup!
[    0.667007] ohci_hcd 0000:03:00.0: init 0000:03:00.0 fail, -19
[    0.669011] ohci_hcd 0000:03:00.1: can't find IRQ for PCI INT D; probably buggy MP table
[    0.670007] ohci_hcd 0000:03:00.1: Found HC with no IRQ.  Check BIOS/PCI 0000:03:00.1 setup!
[    0.671006] ohci_hcd 0000:03:00.1: init 0000:03:00.1 fail, -19
[    0.672022] uhci_hcd: USB Universal Host Controller Interface driver
[    0.679065] Initializing USB Mass Storage driver...
[    0.684027] usbcore: registered new interface driver usb-storage
[    0.690004] USB Mass Storage support registered.
[    0.695025] usbcore: registered new interface driver libusual
[    0.701021] usbcore: registered new interface driver ums-alauda
[    0.707019] usbcore: registered new interface driver ums-cypress
[    0.713019] usbcore: registered new interface driver ums-datafab
[    0.720019] usbcore: registered new interface driver ums-freecom
[    0.726019] usbcore: registered new interface driver ums-isd200
[    0.732029] usbcore: registered new interface driver ums-jumpshot
[    0.738019] usbcore: registered new interface driver ums-karma
[    0.744019] usbcore: registered new interface driver ums-onetouch
[    0.751019] usbcore: registered new interface driver ums-sddr09
[    0.757020] usbcore: registered new interface driver ums-sddr55
[    0.765019] usbcore: registered new interface driver ums-usbat
[    0.771060] PNP: No PS/2 controller found. Probing ports directly.
[    1.028364] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.034119] mice: PS/2 mouse device common for all mice
[    1.039131] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    1.046046] rtc0: alarms up to one day, 114 bytes nvram
[    1.052018] cpuidle: using governor ladder
[    1.056004] cpuidle: using governor menu
[    1.060406] usbcore: registered new interface driver hiddev
[    1.066025] usbcore: registered new interface driver usbhid
[    1.067095] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
[    1.081006] usbhid: v2.6:USB HID core driver
[    1.210416] TCP cubic registered
[    1.214130] NET: Registered protocol family 10
[    1.219588] lo: Disabled Privacy Extensions
[    1.224733] lib80211: common routines for IEEE802.11 drivers
[    1.231225] registered taskstats version 1
[    1.235271]   Magic number: 10:302:959
[    1.240044] pci 0000:00:04.3: hash matches
[    1.244045] rtc_cmos rtc_cmos: setting system clock to 2010-05-13 23:54:33 UTC (1273794873)
[    1.253112] md: Waiting for all devices to be available before autodetect
[    1.260007] md: If you don't use raid, use raid=noautodetect
[    1.266236] md: Autodetecting RAID arrays.
[    1.270004] md: Scanned 0 and added 0 devices.
[    1.275003] md: autorun ...
[    1.278003] md: ... autorun DONE.
[    1.281117] VFS: Cannot open root device "hda3" or unknown-block(0,0)
[    1.288004] Please append a correct "root=" boot option; here are the available partitions:
[    1.296004] DEBUG_BLOCK_EXT_DEVT is enabled, you need to specify explicit textual name for "root=" boot option.
[    1.307004] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[    1.315006] Pid: 1, comm: swapper Not tainted 2.6.31.12-0.2-desktop #1
[    1.322003] Call Trace:
[    1.325031]  [<ffffffff81011a19>] try_stack_unwind+0x189/0x1b0
[    1.331009]  [<ffffffff8101025d>] dump_trace+0xad/0x3a0
[    1.336008]  [<ffffffff81011524>] show_trace_log_lvl+0x64/0x90
[    1.342008]  [<ffffffff81011573>] show_trace+0x23/0x40
[    1.347010]  [<ffffffff81552b46>] dump_stack+0x81/0x9e
[    1.353008]  [<ffffffff81552bf5>] panic+0x92/0x193
[    1.358011]  [<ffffffff819d3a43>] mount_block_root+0x1f8/0x2ac
[    1.364008]  [<ffffffff819d3b5c>] mount_root+0x65/0x80
[    1.369008]  [<ffffffff819d3cc4>] prepare_namespace+0x14d/0x19d
[    1.375008]  [<ffffffff819d2fea>] kernel_init+0xc1/0xe3
[    1.381007]  [<ffffffff8100d7ba>] child_rip+0xa/0x20

Joop Boonen - 2010-05-19 22:18:16
On Thu, May 20, 2010 12:02 am, Joop Boonen wrote:
> On Wed, May 19, 2010 10:29 pm, Stefan Reinauer wrote:
>> Hi,
>>
>> I cleaned up the structures used for Linux booting in FILO, to match
>> what Linux uses these days and moved the structure definitions to a
>> separate (include) file.
>> Also fill in 16MB alignment to fix 2.6.31.. untested...
>
> I've just tested the patch. It looks like it works perfectly.
>
> I've attached the session log.
>
> It only fails because the sil3114 driver isn't loaded it's in the initrd
> file.
>
> I didn't find the option how to define initrd in the filo command line.

I found the option, I've added initrd=hda1:/initrd

Now the kernel boots but hangs on udev. I have to check what the issue is.

The patch seems to be working perfectly.

Thank you.

I didn't create a session log for this boot.
>
>>
>> Best regards,
>> Stefan
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
Joseph Smith - 2010-05-19 22:23:53
On 05/19/2010 06:02 PM, Joop Boonen wrote:
> On Wed, May 19, 2010 10:29 pm, Stefan Reinauer wrote:
>> Hi,
>>
>> I cleaned up the structures used for Linux booting in FILO, to match
>> what Linux uses these days and moved the structure definitions to a
>> separate (include) file.
>> Also fill in 16MB alignment to fix 2.6.31.. untested...
>
> I've just tested the patch. It looks like it works perfectly.
>
> I've attached the session log.
>
> It only fails because the sil3114 driver isn't loaded it's in the initrd
> file.
>
> I didn't find the option how to define initrd in the filo command line.
>
http://www.coreboot.org/FILO#Grub-like_Interface
Myles Watson - 2010-05-19 22:26:06
On Wed, May 19, 2010 at 2:29 PM, Stefan Reinauer <stepan@coresystems.de> wrote:
> Hi,
>
> I cleaned up the structures used for Linux booting in FILO, to match what
> Linux uses these days and moved the structure definitions to a separate
> (include) file.
> Also fill in 16MB alignment to fix 2.6.31.. untested...

Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles
Kevin O'Connor - 2010-05-20 00:43:18
On Thu, May 20, 2010 at 12:02:12AM +0200, Joop Boonen wrote:
> On Wed, May 19, 2010 10:29 pm, Stefan Reinauer wrote:
> > Also fill in 16MB alignment to fix 2.6.31.. untested...
> 
> I've just tested the patch. It looks like it works perfectly.

If you get a chance, run a timing test.  Grab the readserial tool from
the latest seabios git and run on your host:

git clone git://git.linuxtogo.org/home/kevin/seabios.git
./seabios/tools/readserial.py /dev/ttyS0

(You'll need to replace "ttyS0" with your serial device.)

The above tool will time the serial responses - just boot your target
machine and post the log.

-Kevin

Patch

Index: i386/linux_load.c
===================================================================
--- i386/linux_load.c	(revision 131)
+++ i386/linux_load.c	(working copy)
@@ -21,7 +21,6 @@ 
  *
  * Based on work by Steve Gehlbach.
  * Portions are taken from mkelfImage.
- *
  * 2003-09 by SONE Takeshi
  */
 
@@ -36,145 +35,12 @@ 
 #define DEBUG_THIS CONFIG_DEBUG_LINUXLOAD
 #include <debug.h>
 
-#define LINUX_PARAM_LOC 0x90000
-#define COMMAND_LINE_LOC 0x91000
-#define GDT_LOC 0x92000
-#define STACK_LOC 0x93000
+#include "linux_load.h"
 
-#define E820MAX	32		/* number of entries in E820MAP */
-struct e820entry {
-	unsigned long long addr;	/* start of memory segment */
-	unsigned long long size;	/* size of memory segment */
-	unsigned long type;	/* type of memory segment */
-#define E820_RAM	1
-#define E820_RESERVED	2
-#define E820_ACPI	3	/* usable as RAM once ACPI tables have been read */
-#define E820_NVS	4
-};
-
-/* The header of Linux/i386 kernel */
-struct linux_header {
-	u8 reserved1[0x1f1];	/* 0x000 */
-	u8 setup_sects;		/* 0x1f1 */
-	u16 root_flags;		/* 0x1f2 */
-	u8 reserved2[6];	/* 0x1f4 */
-	u16 vid_mode;		/* 0x1fa */
-	u16 root_dev;		/* 0x1fc */
-	u16 boot_sector_magic;	/* 0x1fe */
-	/* 2.00+ */
-	u8 reserved3[2];	/* 0x200 */
-	u8 header_magic[4];	/* 0x202 */
-	u16 protocol_version;	/* 0x206 */
-	u32 realmode_swtch;	/* 0x208 */
-	u16 start_sys;		/* 0x20c */
-	u16 kver_addr;		/* 0x20e */
-	u8 type_of_loader;	/* 0x210 */
-	u8 loadflags;		/* 0x211 */
-	u16 setup_move_size;	/* 0x212 */
-	u32 code32_start;	/* 0x214 */
-	u32 ramdisk_image;	/* 0x218 */
-	u32 ramdisk_size;	/* 0x21c */
-	u8 reserved4[4];	/* 0x220 */
-	/* 2.01+ */
-	u16 heap_end_ptr;	/* 0x224 */
-	u8 reserved5[2];	/* 0x226 */
-	/* 2.02+ */
-	u32 cmd_line_ptr;	/* 0x228 */
-	/* 2.03+ */
-	u32 initrd_addr_max;	/* 0x22c */
-} __attribute__ ((packed));
-
-/* Paramters passed to 32-bit part of Linux
- * This is another view of the structure above.. */
-struct linux_params {
-	u8 orig_x;		/* 0x00 */
-	u8 orig_y;		/* 0x01 */
-	u16 ext_mem_k;		/* 0x02 -- EXT_MEM_K sits here */
-	u16 orig_video_page;	/* 0x04 */
-	u8 orig_video_mode;	/* 0x06 */
-	u8 orig_video_cols;	/* 0x07 */
-	u16 unused2;		/* 0x08 */
-	u16 orig_video_ega_bx;	/* 0x0a */
-	u16 unused3;		/* 0x0c */
-	u8 orig_video_lines;	/* 0x0e */
-	u8 orig_video_isVGA;	/* 0x0f */
-	u16 orig_video_points;	/* 0x10 */
-
-	/* VESA graphic mode -- linear frame buffer */
-	u16 lfb_width;		/* 0x12 */
-	u16 lfb_height;		/* 0x14 */
-	u16 lfb_depth;		/* 0x16 */
-	u32 lfb_base;		/* 0x18 */
-	u32 lfb_size;		/* 0x1c */
-	u16 cl_magic;		/* 0x20 */
-#define CL_MAGIC_VALUE 0xA33F
-	u16 cl_offset;		/* 0x22 */
-	u16 lfb_linelength;	/* 0x24 */
-	u8 red_size;		/* 0x26 */
-	u8 red_pos;		/* 0x27 */
-	u8 green_size;		/* 0x28 */
-	u8 green_pos;		/* 0x29 */
-	u8 blue_size;		/* 0x2a */
-	u8 blue_pos;		/* 0x2b */
-	u8 rsvd_size;		/* 0x2c */
-	u8 rsvd_pos;		/* 0x2d */
-	u16 vesapm_seg;		/* 0x2e */
-	u16 vesapm_off;		/* 0x30 */
-	u16 pages;		/* 0x32 */
-	u8 reserved4[12];	/* 0x34 -- 0x3f reserved for future expansion */
-
-	//struct apm_bios_info apm_bios_info;   /* 0x40 */
-	u8 apm_bios_info[0x40];
-	//struct drive_info_struct drive_info;  /* 0x80 */
-	u8 drive_info[0x20];
-	//struct sys_desc_table sys_desc_table; /* 0xa0 */
-	u8 sys_desc_table[0x140];
-	u32 alt_mem_k;		/* 0x1e0 */
-	u8 reserved5[4];	/* 0x1e4 */
-	u8 e820_map_nr;		/* 0x1e8 */
-	u8 reserved6[9];	/* 0x1e9 */
-	u16 mount_root_rdonly;	/* 0x1f2 */
-	u8 reserved7[4];	/* 0x1f4 */
-	u16 ramdisk_flags;	/* 0x1f8 */
-#define RAMDISK_IMAGE_START_MASK  	0x07FF
-#define RAMDISK_PROMPT_FLAG		0x8000
-#define RAMDISK_LOAD_FLAG		0x4000
-	u8 reserved8[2];	/* 0x1fa */
-	u16 orig_root_dev;	/* 0x1fc */
-	u8 reserved9[1];	/* 0x1fe */
-	u8 aux_device_info;	/* 0x1ff */
-	u8 reserved10[2];	/* 0x200 */
-	u8 param_block_signature[4];	/* 0x202 */
-	u16 param_block_version;	/* 0x206 */
-	u8 reserved11[8];	/* 0x208 */
-	u8 loader_type;		/* 0x210 */
-#define LOADER_TYPE_LOADLIN         1
-#define LOADER_TYPE_BOOTSECT_LOADER 2
-#define LOADER_TYPE_SYSLINUX        3
-#define LOADER_TYPE_ETHERBOOT       4
-#define LOADER_TYPE_KERNEL          5
-	u8 loader_flags;	/* 0x211 */
-	u8 reserved12[2];	/* 0x212 */
-	u32 kernel_start;	/* 0x214 */
-	u32 initrd_start;	/* 0x218 */
-	u32 initrd_size;	/* 0x21c */
-	u8 reserved12_5[8];	/* 0x220 */
-	u32 cmd_line_ptr;	/* 0x228 */
-	u8 reserved13[164];	/* 0x22c */
-	struct e820entry e820_map[E820MAX];	/* 0x2d0 */
-	u8 reserved16[688];	/* 0x550 */
-#define COMMAND_LINE_SIZE 256
-	/* Command line is copied here by 32-bit i386/kernel/head.S.
-	 * So I will follow the boot protocol, rather than putting it
-	 * directly here. --ts1 */
-	u8 command_line[COMMAND_LINE_SIZE];	/* 0x800 */
-	u8 reserved17[1792];	/* 0x900 - 0x1000 */
-};
-
 u64 forced_memsize;
 
 /* Load the first part the file and check if it's Linux */
-static u32 load_linux_header(struct linux_header *hdr)
+static u32 load_linux_header(struct linux_params *hdr)
 {
 	int load_high;
 	u32 kern_addr;
@@ -184,16 +50,16 @@ 
 		return 0;
 	}
 
-	if (hdr->boot_sector_magic != 0xaa55) {
+	if (hdr->hdr.boot_flag != 0xaa55) {
 		printf("Not a Linux kernel image\n");
 		return 0;
 	}
 
 	/* Linux is found. Print some information */
-	if (memcmp(hdr->header_magic, "HdrS", 4) != 0) {
+	if (memcmp(hdr->hdr.header, "HdrS", 4) != 0) {
 		/* This may be floppy disk image or something.
 		 * Perform a simple (incomplete) sanity check. */
-		if (hdr->setup_sects >= 16 || file_size() - (hdr->setup_sects << 9) >= 512 << 10) {
+		if (hdr->hdr.setup_sects >= 16 || file_size() - (hdr->hdr.setup_sects << 9) >= 512 << 10) {
 			printf("This looks like a bootdisk image but not like Linux...\n");
 			return 0;
 		}
@@ -201,14 +67,14 @@ 
 		printf("Possible very old Linux");
 		/* This kernel does not even have a protocol version.
 		 * Force the value. */
-		hdr->protocol_version = 0;	/* pre-2.00 */
+		hdr->hdr.version = 0;	/* pre-2.00 */
 	} else {
 		printf("Found Linux");
 	}
 
-	if (hdr->protocol_version >= 0x200 && hdr->kver_addr) {
+	if (hdr->hdr.version >= 0x200 && hdr->hdr.kernel_version) {
 		char kver[256];
-		file_seek(hdr->kver_addr + 0x200);
+		file_seek(hdr->hdr.kernel_version + 0x200);
 		if (file_read(kver, sizeof kver) != 0) {
 			kver[255] = 0;
 			printf(" version %s", kver);
@@ -217,9 +83,9 @@ 
 	debug(" (protocol %#x)", hdr->protocol_version);
 
 	load_high = 0;
-	if (hdr->protocol_version >= 0x200) {
-		debug(" (loadflags %#x)", hdr->loadflags);
-		load_high = hdr->loadflags & 1;
+	if (hdr->hdr.version >= 0x200) {
+		debug(" (loadflags %#x)", hdr->hdr.loadflags);
+		load_high = hdr->hdr.loadflags & 1;
 	}
 	if (load_high) {
 		printf(" bzImage");
@@ -236,27 +102,30 @@ 
 
 /* Set up parameters for 32-bit kernel */
 static void
-init_linux_params(struct linux_params *params, struct linux_header *hdr)
+init_linux_params(struct linux_params *params, struct linux_params *hdr)
 {
 	debug("Setting up paramters at %#lx\n", virt_to_phys(params));
 	memset(params, 0, sizeof *params);
 
 	/* Copy some useful values from header */
-	params->mount_root_rdonly = hdr->root_flags;
-	params->orig_root_dev = hdr->root_dev;
+	params->hdr.root_flags = hdr->hdr.root_flags;
+	params->hdr.root_dev = hdr->hdr.root_dev;
 
 	/* Video parameters.
 	 * This assumes we have VGA in standard 80x25 text mode,
 	 * just like our vga.c does.
 	 * Cursor position is filled later to allow some more printf's.
 	 */
-	params->orig_video_mode = 3;
-	params->orig_video_cols = 80;
-	params->orig_video_lines = 25;
-	params->orig_video_isVGA = 1;
-	params->orig_video_points = 16;
+	params->screen_info.orig_video_mode = 3;
+	params->screen_info.orig_video_cols = 80;
+	params->screen_info.orig_video_lines = 25;
+	params->screen_info.orig_video_isVGA = 1;
+	params->screen_info.orig_video_points = 16;
 
-	params->loader_type = 0xff;	/* Unregistered Linux loader */
+	params->hdr.loader_type = 0xff;	/* Unregistered Linux loader */
+
+	/* Set it to 16M instead of 4G */
+	params->hdr.kernel_alignment = 16*1024*1024;
 }
 
 /* Memory map */
@@ -280,7 +149,7 @@ 
 			debug("%016Lx - %016Lx (%d)\n", linux_map->addr,
 			      linux_map->addr + linux_map->size,
 			      linux_map->type);
-			params->e820_map_nr = i + 1;
+			params->e820_entries = i + 1;
 		}
 
 		/* Find out top of RAM. XXX This ignores hole above 1MB */
@@ -296,37 +165,39 @@ 
 	params->alt_mem_k = (ramtop - (1 << 20)) >> 10;
 	/* old style, 64MB max */
 	if (ramtop >= (64 << 20))
-		params->ext_mem_k = (63 << 10);
+		params->screen_info.ext_mem_k = (63 << 10);
 	else
-		params->ext_mem_k = params->alt_mem_k;
-	debug("ext_mem_k=%d, alt_mem_k=%d\n", params->ext_mem_k,
-	      params->alt_mem_k);
+		params->screen_info.ext_mem_k = params->alt_mem_k;
+	debug("ext_mem_k=%d, alt_mem_k=%d\n", params->screen_info.ext_mem_k,
+	      params->screen_info.alt_mem_k);
 }
 
 /* Video mode */
 static void set_video_mode(struct linux_params *params)
 {
 #if CONFIG_COREBOOT_VIDEO_CONSOLE
+	struct screen_info *screen_info = &params->screen_info;
+
 	/* Are we running on a framebuffer console? */
 	if (!lib_sysinfo.framebuffer)
 		return;
 
-	params->lfb_width = lib_sysinfo.framebuffer->x_resolution;
-	params->lfb_height = lib_sysinfo.framebuffer->y_resolution;
-	params->lfb_depth = lib_sysinfo.framebuffer->bits_per_pixel;
-	params->lfb_linelength = lib_sysinfo.framebuffer->bytes_per_line;
-	params->lfb_base = lib_sysinfo.framebuffer->physical_address;
+	screen_info->lfb_width = lib_sysinfo.framebuffer->x_resolution;
+	screen_info->lfb_height = lib_sysinfo.framebuffer->y_resolution;
+	screen_info->lfb_depth = lib_sysinfo.framebuffer->bits_per_pixel;
+	screen_info->lfb_linelength = lib_sysinfo.framebuffer->bytes_per_line;
+	screen_info->lfb_base = lib_sysinfo.framebuffer->physical_address;
 	// prolly not enough for the boot splash?!
-	params->lfb_size =
-	    (params->lfb_linelength * params->lfb_height + 65535) >> 16;
-	params->red_size = lib_sysinfo.framebuffer->red_mask_size;
-	params->red_pos = lib_sysinfo.framebuffer->red_mask_pos;
-	params->green_size = lib_sysinfo.framebuffer->green_mask_size;
-	params->green_pos = lib_sysinfo.framebuffer->green_mask_pos;
-	params->blue_size = lib_sysinfo.framebuffer->blue_mask_size;
-	params->blue_pos = lib_sysinfo.framebuffer->blue_mask_pos;
-	params->rsvd_size = lib_sysinfo.framebuffer->reserved_mask_size;
-	params->rsvd_pos = lib_sysinfo.framebuffer->reserved_mask_pos;
+	screen_info->lfb_size =
+	    (screen_info->lfb_linelength * screen_info->lfb_height + 65535) >> 16;
+	screen_info->red_size = lib_sysinfo.framebuffer->red_mask_size;
+	screen_info->red_pos = lib_sysinfo.framebuffer->red_mask_pos;
+	screen_info->green_size = lib_sysinfo.framebuffer->green_mask_size;
+	screen_info->green_pos = lib_sysinfo.framebuffer->green_mask_pos;
+	screen_info->blue_size = lib_sysinfo.framebuffer->blue_mask_size;
+	screen_info->blue_pos = lib_sysinfo.framebuffer->blue_mask_pos;
+	screen_info->rsvd_size = lib_sysinfo.framebuffer->reserved_mask_size;
+	screen_info->rsvd_pos = lib_sysinfo.framebuffer->reserved_mask_pos;
 #endif
 }
 
@@ -455,26 +326,26 @@ 
 
 /* Set command line location */
 static void set_command_line_loc(struct linux_params *params,
-				 struct linux_header *hdr)
+				 struct linux_params *hdr)
 {
-	if (hdr->protocol_version >= 0x202) {
+	if (hdr->hdr.version >= 0x202) {
 		/* new style */
-		params->cmd_line_ptr = COMMAND_LINE_LOC;
+		params->hdr.cmd_line_ptr = COMMAND_LINE_LOC;
 	} else {
 		/* old style */
-		params->cl_magic = CL_MAGIC_VALUE;
-		params->cl_offset = COMMAND_LINE_LOC - LINUX_PARAM_LOC;
+		params->screen_info.cl_magic = CL_MAGIC_VALUE;
+		params->screen_info.cl_offset = COMMAND_LINE_LOC - LINUX_PARAM_LOC;
 	}
 }
 
 /* Load 32-bit part of kernel */
-static int load_linux_kernel(struct linux_header *hdr, u32 kern_addr)
+static int load_linux_kernel(struct linux_params *hdr, u32 kern_addr)
 {
 	u32 kern_offset, kern_size;
 
-	if (hdr->setup_sects == 0)
-		hdr->setup_sects = 4;
-	kern_offset = (hdr->setup_sects + 1) * 512;
+	if (hdr->hdr.setup_sects == 0)
+		hdr->hdr.setup_sects = 4;
+	kern_offset = (hdr->hdr.setup_sects + 1) * 512;
 	file_seek(kern_offset);
 	kern_size = file_size() - kern_offset;
 	debug("offset=%#x addr=%#x size=%#x\n", kern_offset, kern_addr,
@@ -496,7 +367,7 @@ 
 	return kern_size;
 }
 
-static int load_initrd(struct linux_header *hdr,
+static int load_initrd(struct linux_params *hdr,
 		       u32 kern_end, struct linux_params *params,
 		       const char *initrd_file)
 {
@@ -522,8 +393,8 @@ 
 
 	/* Find out the kernel's restriction on how high the initrd can be
 	 * placed */
-	if (hdr->protocol_version >= 0x203)
-		max = hdr->initrd_addr_max;
+	if (hdr->hdr.version >= 0x203)
+		max = hdr->hdr.ramdisk_max;
 	else
 		max = 0x38000000;	/* Hardcoded value for older kernels */
 
@@ -586,8 +457,8 @@ 
 	}
 	printf("ok\n");
 
-	params->initrd_start = start;
-	params->initrd_size = size;
+	params->hdr.ramdisk_start = start;
+	params->hdr.ramdisk_size = size;
 
 	return 0;
 }
@@ -680,8 +551,8 @@ 
 	/* Update VGA cursor position.
 	 * This must be here because the printf changes the value! */
 	video_console_get_cursor(&cursor_x, &cursor_y, &cursor_en);
-	params->orig_x = cursor_x;
-	params->orig_y = cursor_y;
+	params->screen_info.orig_x = cursor_x;
+	params->screen_info.orig_y = cursor_y;
 #endif
 
 #ifdef CONFIG_PCMCIA_CF
@@ -701,7 +572,7 @@ 
 
 int linux_load(const char *file, const char *cmdline)
 {
-	struct linux_header hdr;
+	static struct linux_params hdr;
 	struct linux_params *params;
 	u32 kern_addr, kern_size;
 	char *initrd_file = 0;
Index: i386/linux_load.h
===================================================================
--- i386/linux_load.h	(revision 0)
+++ i386/linux_load.h	(revision 0)
@@ -0,0 +1,213 @@ 
+/*
+ * This file is part of FILO.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <libpayload.h>
+
+#define COMMAND_LINE_SIZE 256
+
+#define LINUX_PARAM_LOC  0x90000
+#define COMMAND_LINE_LOC 0x91000
+#define GDT_LOC		 0x92000
+#define STACK_LOC	 0x93000
+
+#define EDD_MBR_SIG_MAX	16	
+#define E820MAX		128	/* number of entries in E820MAP */
+struct e820entry {
+	u64 addr;	/* start of memory segment */
+	u64 size;	/* size of memory segment */
+	u32 type;	/* type of memory segment */
+#define E820_RAM	1
+#define E820_RESERVED	2
+#define E820_ACPI	3	/* usable as RAM once ACPI tables have been read */
+#define E820_NVS	4
+#define E820_UNUSABLE	5
+};
+
+struct screen_info {
+	u8  orig_x;			/* 0x00 */
+	u8  orig_y;			/* 0x01 */
+	u16 ext_mem_k;			/* 0x02 */
+	u16 orig_video_page;		/* 0x04 */
+	u8  orig_video_mode;		/* 0x06 */
+	u8  orig_video_cols;		/* 0x07 */
+	u16 unused2;			/* 0x08 */
+	u16 orig_video_ega_bx;		/* 0x0a */
+	u16 unused3;			/* 0x0c */
+	u8  orig_video_lines;		/* 0x0e */
+	u8  orig_video_isVGA;		/* 0x0f */
+	u16 orig_video_points;		/* 0x10 */
+
+	/* VESA graphic mode -- linear frame buffer */
+	u16 lfb_width;			/* 0x12 */
+	u16 lfb_height;			/* 0x14 */
+	u16 lfb_depth;			/* 0x16 */
+	u32 lfb_base;			/* 0x18 */
+	u32 lfb_size;			/* 0x1c */
+	u16 cl_magic;			/* 0x20 */
+#define CL_MAGIC_VALUE 0xA33F
+	u16 cl_offset;			/* 0x22 */
+	u16 lfb_linelength;		/* 0x24 */
+	u8  red_size;			/* 0x26 */
+	u8  red_pos;			/* 0x27 */
+	u8  green_size;			/* 0x28 */
+	u8  green_pos;			/* 0x29 */
+	u8  blue_size;			/* 0x2a */
+	u8  blue_pos;			/* 0x2b */
+	u8  rsvd_size;			/* 0x2c */
+	u8  rsvd_pos;			/* 0x2d */
+	u16 vesapm_seg;			/* 0x2e */
+	u16 vesapm_off;			/* 0x30 */
+	u16 pages;			/* 0x32 */
+	u16 vesa_attributes;		/* 0x34 */
+	u32 capabilities;		/* 0x36 */
+	u8  reserved[6];		/* 0x3a -- 0x3f reserved for future expansion */
+} __attribute__((packed));
+
+struct apm_bios_info {
+	u8  reserved[0x14];
+} __attribute__((packed));
+
+struct ist_info {
+	u8  reserved[0x10];
+} __attribute__((packed));
+
+struct sys_desc_table {
+	u16 length;
+	u8  reserved[14];
+} __attribute__((packed));
+
+struct edid_info {
+	u8  reserved[0x1c0 - 0x140];
+} __attribute__((packed));
+
+struct efi_info {
+	u32 efi_loader_signature;
+	u32 efi_systab;
+	u32 efi_memdesc_size;
+	u32 efi_memdesc_version;
+	u32 efi_memmap;
+	u32 efi_memmap_size;
+	u32 efi_systab_hi;
+	u32 efi_memmap_hi;
+} __attribute__((packed));
+
+struct edd_device_params {
+	u8 reserved[74];
+} __attribute__((packed));
+
+#define EDDMAXNR 6
+struct edd_info {
+	u8  device;
+	u8  version;
+	u16 interface_support;
+	u16 legacy_max_cylinder;
+	u8  legacy_max_head;
+	u8  legacy_sectors_per_track;
+	struct edd_device_params params;
+} __attribute__((packed));
+
+struct setup_header {
+	/* Documentation/x86/boot.txt starts here */
+	u8  setup_sects;		/* 0x1f1 */
+	u16 root_flags;			/* 0x1f2 */
+	u32 syssize;			/* 0x1f4 */
+	u16 ram_size;			/* 0x1f8 */
+#define RAMDISK_IMAGE_START_MASK  	0x07FF
+#define RAMDISK_PROMPT_FLAG		0x8000
+#define RAMDISK_LOAD_FLAG		0x4000
+	u16 vid_mode;			/* 0x1fa */
+	u16 root_dev;			/* 0x1fc */
+	u16 boot_flag;			/* 0x1fe */
+	u16 jump;			/* 0x200 */
+	u8  header[4];			/* 0x202 */
+	u16 version;			/* 0x206 */
+	u32 realmode_swtch;		/* 0x208 */
+	u16 start_sys_seg;		/* 0x20c */
+	u16 kernel_version;		/* 0x20e */
+	u8  loader_type;		/* 0x210 */
+#define LOADER_TYPE_LOADLIN         	0x1
+#define LOADER_TYPE_BOOTSECT_LOADER 	0x2
+#define LOADER_TYPE_SYSLINUX        	0x3
+#define LOADER_TYPE_ETHERBOOT       	0x4
+#define LOADER_TYPE_KERNEL          	0x5
+	u8  loadflags;			/* 0x211 */
+#define LOADED_HIGH			(1 << 0)
+#define QUIET_FLAG			(1 << 5)
+#define KEEP_SEGMENTS			(1 << 6)
+#define CAN_USE_HEAP			(1 << 7)
+	u16 setup_move_size;		/* 0x212 */
+	u32 code32_start;		/* 0x214 */
+	u32 ramdisk_start;		/* 0x218 */
+	u32 ramdisk_size;		/* 0x21c */
+	u32 bootsect_kludge;		/* 0x220 */
+	/* 2.01+ */
+	u16 heap_end_ptr;		/* 0x224 */
+	/* 2.02+ */
+	u8  ext_loader_ver;		/* 0x226 */
+	u8  ext_loader_type;		/* 0x227 */
+	u32 cmd_line_ptr;		/* 0x228 */
+	/* 2.03+ */
+	u32 ramdisk_max;		/* 0x22c */
+	/* 2.05+ */
+	u32 kernel_alignment;		/* 0x230 */
+	u8  relocatable_kernel;		/* 0x234 */
+	/* 2.10+ */
+	u8 min_alignment;		/* 0x235 */
+	u8 reserved[2];			/* 0x236 */
+	/* 2.06+ */
+	u32 cmdlinux_size;		/* 0x238 */
+	/* 2.07+ */
+	u32 hardware_subarch;		/* 0x23c */
+	u64  hardware_subarch_data;	/* 0x240 */
+	/* 2.08+ */
+	u32 payload_offset;		/* 0x248 */
+	u32 payload_length;		/* 0x24c */
+	/* 2.09+ */
+	u64 setup_data;			/* 0x250 */
+	/* 2.10+ */
+	u64 pref_address;		/* 0x258 */
+	u32 init_size;			/* 0x260 */
+} __attribute__((packed));
+
+/* Paramters passed to 32-bit part of Linux */
+struct linux_params {
+	struct screen_info screen_info;		/* 0x000 */
+	struct apm_bios_info apm_bios_info;	/* 0x040 */
+	u8  reserved1[0x60 - 0x54];
+	struct ist_info ist_info;		/* 0x060 */
+	u8  reserved2[0x80 - 0x70];
+	u8  hd0_info[0x10];			/* 0x080 */
+	u8  hd1_info[0x10];			/* 0x090 */
+	struct sys_desc_table sys_desc_table;	/* 0x0a0 */
+	u8  reserved3[0x140 - 0xb0];
+	struct edid_info edid_info;		/* 0x140 */
+	struct efi_info efi_info;		/* 0x1c0 */
+	u32 alt_mem_k;				/* 0x1e0 */
+	u32 scratch;				/* 0x1e4 */
+	u8  e820_entries;			/* 0x1e8 */
+	u8  eddbuf_entries;			/* 0x1e9 */
+	u8  edd_mbr_sig_buf_entries;		/* 0x1ea */
+	u8  reserved4[0x1f1-0x1eb];
+	struct setup_header hdr;		/* 0x1f1 */
+	u8  reserved5[0x290-0x1f1-sizeof(struct setup_header)];
+	u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX];/* 0x290 */
+	struct e820entry e820_map[E820MAX];	/* 0x2d0 */
+	u8  reserved7[0xd00 - 0xcd0];
+	struct edd_info eddbuf[EDDMAXNR];	/* 0xd00 */
+	u8  reserved8[0x1000 - 0xeec];
+} __attribute__((packed));
+