Patchwork [RFC] change the ROM caching for AMD CAR

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Submitter Rudolf Marek
Date 2010-05-23 09:38:38
Message ID <4BF8F79E.2070508@assembler.cz>
Download mbox | patch
Permalink /patch/1375/
State New
Headers show

Comments

Rudolf Marek - 2010-05-23 09:38:38
Hi all,

It looks like we can cache now the whole ROM while in CAR (i showed that in the 
analysis posted earlier, it works too ;)

The attached patch does that. Comments?

Marc and I thinks we can add some safeguard to check if any L2 data was evicted 
during CAR to RAM. This is just few instructions to enable the PerfCounter and
then  read it in the post_cache_as_ram. I will post this as separate patch.


Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

I did not test this particular patch however it does work with similar changes 
already. I take this patch as think for RFC, if it is enough to change it like this.

Thanks,
Rudolf
Stefan Reinauer - 2010-05-23 10:05:31
On 5/23/10 11:38 AM, Rudolf Marek wrote:
> Hi all,
>
> It looks like we can cache now the whole ROM while in CAR (i showed
> that in the analysis posted earlier, it works too ;)
>
> The attached patch does that. Comments?
>
> Marc and I thinks we can add some safeguard to check if any L2 data
> was evicted during CAR to RAM. This is just few instructions to enable
> the PerfCounter and
> then  read it in the post_cache_as_ram. I will post this as separate
> patch.
>
>
> Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
>
> I did not test this particular patch however it does work with similar
> changes already. I take this patch as think for RFC, if it is enough
> to change it like this.
>
Does this fix the slowness of copying coreboot_ram to ram?

Stefan
Marc Jones - 2010-05-28 18:07:35
On Sun, May 23, 2010 at 4:05 AM, Stefan Reinauer
<stefan.reinauer@coresystems.de> wrote:
> On 5/23/10 11:38 AM, Rudolf Marek wrote:
>> Hi all,
>>
>> It looks like we can cache now the whole ROM while in CAR (i showed
>> that in the analysis posted earlier, it works too ;)
>>
>> The attached patch does that. Comments?
>>
>> Marc and I thinks we can add some safeguard to check if any L2 data
>> was evicted during CAR to RAM. This is just few instructions to enable
>> the PerfCounter and
>> then  read it in the post_cache_as_ram. I will post this as separate
>> patch.
>>
>>
>> Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
>>
>> I did not test this particular patch however it does work with similar
>> changes already. I take this patch as think for RFC, if it is enough
>> to change it like this.
>>
> Does this fix the slowness of copying coreboot_ram to ram?

I don't expect this to fix the slow lzma decomress. The disable_car
code still changes the MTRR settings. That needs to be sorted as well.

Marc
Marc Jones - 2010-05-28 18:09:24
2010/5/23 Rudolf Marek <r.marek@assembler.cz>:
> Hi all,
>
> It looks like we can cache now the whole ROM while in CAR (i showed that in
> the analysis posted earlier, it works too ;)
>
> The attached patch does that. Comments?
>
> Marc and I thinks we can add some safeguard to check if any L2 data was
> evicted during CAR to RAM. This is just few instructions to enable the
> PerfCounter and
> then  read it in the post_cache_as_ram. I will post this as separate patch.
>
>
> Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
>
> I did not test this particular patch however it does work with similar
> changes already. I take this patch as think for RFC, if it is enough to
> change it like this.

Rudolf,

I would test and ack a patch with the perfcounter setup in it.

Marc

Patch

Index: src/cpu/amd/socket_AM3/Kconfig
===================================================================
--- src/cpu/amd/socket_AM3/Kconfig	(revision 5555)
+++ src/cpu/amd/socket_AM3/Kconfig	(working copy)
@@ -34,14 +34,3 @@ 
 	hex
 	default 0x18
 	depends on CPU_AMD_SOCKET_AM3
-
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_AM3
-
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-	depends on CPU_AMD_SOCKET_AM3
-
Index: src/cpu/amd/socket_AM2r2/Kconfig
===================================================================
--- src/cpu/amd/socket_AM2r2/Kconfig	(revision 5555)
+++ src/cpu/amd/socket_AM2r2/Kconfig	(working copy)
@@ -34,13 +34,3 @@ 
 	hex
 	default 0x18
 	depends on CPU_AMD_SOCKET_AM2R2
-
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_AM2R2
-
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-	depends on CPU_AMD_SOCKET_AM2R2
Index: src/cpu/amd/socket_ASB2/Kconfig
===================================================================
--- src/cpu/amd/socket_ASB2/Kconfig	(revision 5555)
+++ src/cpu/amd/socket_ASB2/Kconfig	(working copy)
@@ -34,13 +34,3 @@ 
 	hex
 	default 0x18
 	depends on CPU_AMD_SOCKET_ASB2
-
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_ASB2
-
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-	depends on CPU_AMD_SOCKET_ASB2
Index: src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- src/cpu/amd/car/cache_as_ram.inc	(revision 5555)
+++ src/cpu/amd/car/cache_as_ram.inc	(working copy)
@@ -245,20 +245,12 @@ 
 	xorl	%edx, %edx
 	movl	$(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
 	wrmsr
-
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* enable write base caching so we can do execute in place
 	 * on the flash rom.
 	 */
 	movl	$0x202, %ecx
 	xorl	%edx, %edx
-
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-	movl    $REAL_XIP_ROM_BASE, %eax
+	movl    $(0xffffffff - CONFIG_ROM_SIZE + 1), %eax
 	orl     $MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
@@ -267,10 +259,8 @@ 
 	jmp_if_k8(wbcache_post_fam10_setup)
 	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
-
 	/* Set the default memory type and enable fixed and variable MTRRs */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
Index: src/cpu/amd/socket_F_1207/Kconfig
===================================================================
--- src/cpu/amd/socket_F_1207/Kconfig	(revision 5555)
+++ src/cpu/amd/socket_F_1207/Kconfig	(working copy)
@@ -33,13 +33,3 @@ 
 	hex
 	default 0x18
 	depends on CPU_AMD_SOCKET_F_1207
-
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_F_1207
-
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-	depends on CPU_AMD_SOCKET_F_1207
Index: src/mainboard/asus/p2b/romstage.c.orig
===================================================================
Index: src/mainboard/asus/p2b/acpi_tables.c
===================================================================
Index: src/mainboard/asus/p2b/dsdt.asl
===================================================================
Index: src/drivers/Kconfig
===================================================================
Index: src/drivers/si/3114/Makefile.inc
===================================================================