===================================================================
@@ -26,8 +26,10 @@
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
+ select GENERATE_PIRQ_TABLE
+ select PIRQ_ROUTE
select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
+ select DEBUG
config MAINBOARD_DIR
string
@@ -49,3 +51,7 @@
default 6
depends on BOARD_NOKIA_IP530
+config HEAP_SIZE
+ hex
+ default 0x60000
+ depends on BOARD_NOKIA_IP530
===================================================================
@@ -29,17 +29,11 @@
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
device pci 7.0 on # ISA bridge
- chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
+ chip superio/smsc/smscsuperio # Super I/O FDC 37C878
+ device pnp 3f0.0 off # Floppy
+ end
+ device pnp 3f0.3 off # Parallel port
+ end
device pnp 3f0.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
@@ -49,26 +43,21 @@
irq 0x70 = 3
end
device pnp 3f0.7 on # PS/2 keyboard / mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
end
- device pnp 3f0.9 on # Game port
- io 0x60 = 0x201
+ device pnp 3f0.6 on # RTC
+ io 0x62 = 0x0072
+ irq 0x70 = 8
+ irq 0xF0 = 16
end
- device pnp 3f0.a on # Power-management events (PME)
- io 0x60 = 0x600
+ device pnp 3f0.8 on # AUX I/O
end
- device pnp 3f0.b on # MIDI port (MPU-401)
- io 0x60 = 0x330
- irq 0x70 = 5
+ device pnp 3f0.A off # ACPI
end
end
end
device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
+ device pci 7.2 off end # USB
+ device pci 7.3 off end # ACPI
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
@@ -78,17 +67,5 @@
register "ide1_drive0_udma33_enable" = "0"
register "ide1_drive1_udma33_enable" = "0"
end
- device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0f.0 on end # CardBus bridge (TI PCI1225)
- device pci 0f.1 on end # CardBus bridge (TI PCI1225)
end
- device pci_domain 1 on # PCI domain 1
- device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
- end
- device pci_domain 2 on # PCI domain 2
- device pci 04.0 on end # NIC (DECchip 21142/43)
- device pci 04.0 on end # NIC (DECchip 21142/43)
- end
end
-
===================================================================
@@ -26,6 +26,7 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
+#include "pc80/serial.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
===================================================================
@@ -31,15 +31,14 @@
0x122e, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x36, /* Checksum */
+ 0x08, /* Checksum */
{
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
- {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
- {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
- {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
- {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
- {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+ { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0 },
+ { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0 },
+ { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0 },
+ { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0 },
+ { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0 },
}
};
@@ -47,3 +46,11 @@
{
return copy_pirq_routing_table(addr);
}
+
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+ // This is just here as a placeholder until the point is solved in the
+ // main code of coreboot
+ return;
+}
+
===================================================================
@@ -20,7 +20,65 @@
#include <device/device.h>
#include "chip.h"
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#define OUTB outb
+#define INB inb
+/*
+* Taken from flashrom project
+* Generic Super I/O helper functions
+*/
+static uint8_t sio_read(uint16_t port, uint8_t reg)
+{
+ OUTB( reg, port );
+ return ( INB( port + 1 ) );
+}
+
+static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
+{
+ OUTB( reg, port );
+ OUTB( data, port + 1 );
+ return;
+}
+
+static void nokia_ip530_board_enable( device_t dev )
+{
+ print_debug( "Setting up IP530-Super I/O devices\n");
+ /*
+ * Register 03 (Index Address) needs to be set to 0x80:
+ *
+ * Enable GP1, WDT_CTRL, GP5, GP6, Soft Power Enable and Status
+ * Register access when not in configuration mode (0x80)
+ * Sets GP1 etc. selection regis ter used when in Run mode
+ * (not in Configuration Mode), 00 = 0xE0
+ *
+ * Register 22: (Power Control) need to be set to 0x30:
+ *
+ * Serial Port 1 Power, = 1 Power on or enabled (0x10)
+ * Serial Port 2 Power, = 1 Power on or enabled (0x20)
+ * *Note* the rest of the devices are disabled.
+ *
+ * Register 24: ( OSC ) need to be set to 0x84:
+ *
+ * Osc is on, BRG clock is on. (0x04)
+ * IRQ8 Polarity is IRQ8 is active low (0x80)
+ *
+ * This is done outside the config mode
+ */
+ printk( BIOS_DEBUG, "--Correcting direct registers\n");
+ sio_write( 0x20, 0x03, 0x80 );
+ printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
+ sio_write( 0x20, 0x22, 0x30 );
+ printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
+ sio_write( 0x20, 0x24, 0x84 );
+ printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
+ return;
+}
+
struct chip_operations mainboard_ops = {
- CHIP_NAME("Nokia IP530 Mainboard")
+ CHIP_NAME("NOKIA IP530 Mainboard")
+ .enable_dev = nokia_ip530_board_enable,
};
===================================================================
@@ -3,6 +3,8 @@
* Aug 26 2001 , Nikolai Vladychevski, <niko@isl.net.mx>
* 2007.04.09 Jeremy Jackson <jerj@coplanar.net>
* updated for amd64 and general 64 bit portability
+ * 2010.04.24 Marc Bertens <mbertens@xs4all.nl>
+ * Added functionality to read a image file for checking the checksum of the PIR
*/
#include <stdio.h>
@@ -24,27 +26,48 @@
# define MEM_DEV "/dev/mem"
#endif
-static struct irq_routing_table *probe_table(int fd_mem)
+static struct irq_routing_table *probe_table(char* ptr)
{
- char *ptr, signature[] = "$PIR";
- struct irq_routing_table *rt;
+ char signature[] = "$PIR\x00\x01";
+ struct irq_routing_table *rt = (struct irq_routing_table *)ptr;
int size = 16;
-
- ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED,
- fd_mem, (off_t) 0xf0000);
-
- if (ptr == MAP_FAILED) {
- perror("Mapping system memory failed: ");
- return NULL;
- }
-
+ int iResult;
do {
- rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 4);
+ rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 6);
if (rt != NULL) {
- printf("Found PCI IRQ routing table signature at %p.\n",
- (void *) ((char *) rt - ptr + 0xf0000));
- printf("Validating... ");
- if (!calc_checksum(rt)) {
+ int i, ts = (rt->size - 32) / 16;
+ struct irq_info *se_arr;
+ se_arr = (struct irq_info *) ((char *) rt + 32);
+ printf("Found PCI IRQ routing table signature at %p.\n", (void *) ((char *) rt - ptr + 0xf0000));
+ printf("SIGNATURE = %s\n", (char*)&rt->signature);
+ printf("VERSION = %04x\n", rt->version);
+ printf("SIZE = %i\n", rt->size);
+ printf("MAX_DEVICES_ON_BUS = 32 + 16 * %d\n", ts);
+ printf("INT_ROUTER_BUS = 0x%02x\n", rt->rtr_bus);
+ printf("INT_ROUTER DEVICE = (0x%02x << 3) | 0x%01x\n", rt->rtr_devfn >> 3, rt->rtr_devfn & 7);
+ printf("IRQ_DEVOTED_TO_PCI = %#x\n", rt->exclusive_irqs);
+ printf("VENDOR = %#x\n", rt->rtr_vendor);
+ printf("DEVICE = %#x\n", rt->rtr_device);
+ printf("MINIPORT = %#x\n", rt->miniport_data);
+ printf("CHECKSUM = %#x\n", rt->checksum);
+ printf("\tbus , dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu\n");
+ for (i = 0; i < ts; i++) {
+ printf("\t0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n",
+ (se_arr+i)->bus, (se_arr+i)->devfn >> 3,
+ (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link,
+ (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link,
+ (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link,
+ (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link,
+ (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot,
+ (se_arr+i)->rfu);
+ }
+ if (rt->size > 0x400) {
+ return NULL;
+ }
+ printf("Validating...\n");
+ iResult = calc_checksum(rt);
+ printf("CHECKSUM = %#x\n", 0x100-((iResult - rt->checksum) & 0xFF));
+ if (!iResult) {
printf("checksum is ok.\n");
break;
} else {
@@ -56,35 +79,70 @@
if (size >= 0xFFFF) {
printf("No PCI IRQ routing table signature found.\n");
- munmap(ptr, 0x10000);
return NULL;
}
return rt;
}
-int main(void)
+int main(int argc, char* argv[])
{
- int fd_mem;
- struct irq_routing_table *rt;
-
- if (getuid()) {
- fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n");
+ char* ptr;
+ int fd_mem = -1;
+ struct irq_routing_table* rt = NULL;
+ void* pBiosImage = NULL;
+ if ( argc > 1 )
+ {
+ printf("Opening memory image file '%s'\n", argv[1]);
+ fd_mem = open(argv[1], O_RDONLY);
+ if (fd_mem > 0) {
+ int iSize = lseek(fd_mem, 0, SEEK_END);
+ printf("Memory image '%i'\n", iSize);
+ pBiosImage = malloc(iSize);
+ if (pBiosImage) {
+ lseek(fd_mem, 0, SEEK_SET);
+ read(fd_mem, pBiosImage, iSize);
+ ptr = (char*)pBiosImage;
+ } else {
+ perror("Failed to open imagefile\n");
+ return (-3);
+ }
+ } else {
+ perror("Failed to open imagefile");
+ return (-2);
+ }
+ } else {
+ printf("Accessing memory\n");
+ if (getuid()) {
+ fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n");
+ }
+ fd_mem = open(MEM_DEV, O_RDONLY);
+ if (fd_mem < 0) {
+ perror("Could not open " MEM_DEV ":");
+ exit(1);
+ }
+ printf("Probing PIRQ table in memory.\n");
+ ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED, fd_mem, (off_t)0xf0000);
+ if (ptr == MAP_FAILED) {
+ perror("Mapping system memory failed: ");
+ close(fd_mem);
+ return (1);
+ }
}
-
- fd_mem = open(MEM_DEV, O_RDONLY);
- if (fd_mem < 0) {
- perror("Could not open " MEM_DEV ":");
- exit(1);
+ if (ptr) {
+ rt = probe_table(ptr);
+ if (rt != NULL && pBiosImage == NULL) {
+ printf("Creating irq_tables.c ...\n");
+ code_gen("irq_tables.c", rt);
+ printf("Done, you can move the file to the coreboot tree now.\n");
+ }
+ } else {
+ printf("invalid memory pointer\n");
}
-
- printf("Probing PIRQ table in memory.\n");
- rt = probe_table(fd_mem);
- if (rt != NULL) {
- printf("Creating irq_tables.c ...\n");
- code_gen("irq_tables.c", rt);
- printf
- ("Done, you can move the file to the coreboot tree now.\n");
+ if (pBiosImage) {
+ free(pBiosImage);
+ } else {
+ munmap(ptr, 0x10000);
}
close(fd_mem);