===================================================================
@@ -1,454 +1,20 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-//@DOC
-// in amd8132_bridge.c
/*
-$1.0$
-*/
-// Description: amd 8132 support
-// by yhlu
-//
-//============================================================================
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <device/pci_def.h>
-#include <device/pcix.h>
-
-#define NMI_OFF 0
-
-#define NPUML 0xD9 /* Non prefetchable upper memory limit */
-#define NPUMB 0xD8 /* Non prefetchable upper memory base */
-
-static void amd8132_walk_children(struct bus *bus,
- void (*visit)(device_t dev, void *ptr), void *ptr)
-{
- device_t child;
- for(child = bus->children; child; child = child->sibling)
- {
- if (child->path.type != DEVICE_PATH_PCI) {
- continue;
- }
- if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
- amd8132_walk_children(&child->link[0], visit, ptr);
- }
- visit(child, ptr);
- }
-}
-
-struct amd8132_bus_info {
- unsigned sstatus;
- unsigned rev;
- int master_devices;
- int max_func;
-};
-
-static void amd8132_count_dev(device_t dev, void *ptr)
-{
- struct amd8132_bus_info *info = ptr;
- /* Don't count pci bridges */
- if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
- info->master_devices++;
- }
- if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
- info->max_func = PCI_FUNC(dev->path.pci.devfn);
- }
-}
-
-
-static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
-{
- struct amd8132_bus_info *info = ptr;
- unsigned cap;
- unsigned status, cmd, orig_cmd;
- unsigned max_read, max_tran;
- int sibs;
-
- if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
- return;
- }
- cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
- if (!cap) {
- return;
- }
- /* How many siblings does this device have? */
- sibs = info->master_devices - 1;
-
- printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev));
- status = pci_read_config32(dev, cap + PCI_X_STATUS);
- orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
-
- max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
- max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
-
- if (info->rev == 0x01) { // only a1 need it
- /* Errata #53 Limit the number of split transactions to avoid starvation */
- if (sibs >= 2) {
- /* At most 2 outstanding split transactions when we have
- * 3 or more bus master devices on the bus.
- */
- if (max_tran > 1) {
- max_tran = 1;
- }
- }
- else if (sibs == 1) {
- /* At most 4 outstanding split transactions when we have
- * 2 bus master devices on the bus.
- */
- if (max_tran > 3) {
- max_tran = 3;
- }
- }
- else {
- /* At most 8 outstanding split transactions when we have
- * only one bus master device on the bus.
- */
- if (max_tran > 4) {
- max_tran = 4;
- }
- }
- }
-
- if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
- cmd &= ~PCI_X_CMD_MAX_READ;
- cmd |= max_read << 2;
- }
- if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
- cmd &= ~PCI_X_CMD_MAX_SPLIT;
- cmd |= max_tran << 4;
- }
-
- /* Don't attempt to handle PCI-X errors */
- cmd &= ~PCI_X_CMD_DPERR_E;
- if (orig_cmd != cmd) {
- pci_write_config16(dev, cap + PCI_X_CMD, cmd);
- }
-
-
-}
-static unsigned int amd8132_scan_bus(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn, unsigned int max)
-{
- struct amd8132_bus_info info;
- unsigned pos;
-
-
- /* Find the children on the bus */
- max = pci_scan_bus(bus, min_devfn, max_devfn, max);
-
- /* Find the revision of the 8132 */
- info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
-
- /* Find the pcix capability and get the secondary bus status */
- pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
- info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
-
- /* Print the PCI-X bus speed */
- printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
-
-
- /* Examine the bus and find out how loaded it is */
- info.max_func = 0;
- info.master_devices = 0;
- amd8132_walk_children(bus, amd8132_count_dev, &info);
-
-#if 0
- /* Disable the bus if there are no devices on it
- */
- if (!bus->children)
- {
- unsigned pcix_misc;
- /* Disable all of my children */
- disable_children(bus);
-
- /* Remember the device is disabled */
- bus->dev->enabled = 0;
-
- /* Disable the PCI-X clocks */
- pcix_misc = pci_read_config32(bus->dev, 0x40);
- pcix_misc &= ~(0x1f << 16);
- pci_write_config32(bus->dev, 0x40, pcix_misc);
-
- return max;
- }
-#endif
-
- /* If we are in conventional PCI mode nothing more is necessary.
- */
- if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
- return max;
- }
-
- /* Tune the devices on the bus */
- amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
-
- return max;
-}
-
-static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)
-{
- return do_pci_scan_bridge(dev, max, amd8132_scan_bus);
-}
-
-
-static void amd8132_pcix_init(device_t dev)
-{
- uint32_t dword;
- uint8_t byte;
- unsigned chip_rev;
-
- /* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
-
- /* Enable memory write and invalidate ??? */
- dword = pci_read_config32(dev, 0x04);
- dword |= 0x10;
- dword &= ~(1<<6); // PERSP Parity Error Response
- pci_write_config32(dev, 0x04, dword);
-
- if (chip_rev == 0x01) {
- /* Errata #37 */
- byte = pci_read_config8(dev, 0x0c);
- if(byte == 0x08 )
- pci_write_config8(dev, 0x0c, 0x10);
-
-#if 0
- /* Errata #59*/
- dword = pci_read_config32(dev, 0x40);
- dword &= ~(1<<31);
- pci_write_config32(dev, 0x40, dword);
-#endif
-
- }
-
- /* Set up error reporting, enable all */
- /* system error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
-
- /* system and error parity enable */
- dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
-
- dword = pci_read_config32(dev, 0x40);
-// dword &= ~(1<<31); /* WriteChainEnable */
- dword |= (1<<31);
- dword |= (1<<7);// must set to 1
- dword |= (3<<21); //PCIErrorSerrDisable
- pci_write_config32(dev, 0x40, dword);
-
- /* EXTARB = 1, COMPAT = 0 */
- dword = pci_read_config32(dev, 0x48);
- dword |= (1<<3);
- dword &= ~(1<<0);
- dword |= (1<<15); //CLEARPCILOG_L
- dword |= (1<<19); //PERR FATAL Enable
- dword |= (1<<22); // SERR FATAL Enable
- dword |= (1<<23); // LPMARBENABLE
- dword |= (0x61<<24); //LPMARBCOUNT
- pci_write_config32(dev, 0x48, dword);
-
- dword = pci_read_config32(dev, 0x4c);
- dword |= (1<<6); //intial prefetch for memory read line request
- dword |= (1<<9); //continuous prefetch Enable for memory read line request
- pci_write_config32(dev, 0x4c, dword);
-
-
- /* Disable Single-Bit-Error Correction [30] = 0 */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1<<30);
- pci_write_config32(dev, 0x70, dword);
-
- //link
- dword = pci_read_config32(dev, 0xd4);
- dword |= (0x5c<<16);
- pci_write_config32(dev, 0xd4, dword);
-
- /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
- dword = pci_read_config32(dev, 0xdc);
- dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
- dword |= (1<<18)|(1<<26);
- dword &= ~((3<<16)|(3<<24));
- pci_write_config32(dev, 0xdc, dword);
-
- /* Set up CRC flood enable */
- dword = pci_read_config32(dev, 0xc0);
- if(dword) { /* do device A only */
-#if 0
- dword = pci_read_config32(dev, 0xc4);
- dword |= (1<<1);
- pci_write_config32(dev, 0xc4, dword);
- dword = pci_read_config32(dev, 0xc8);
- dword |= (1<<1);
- pci_write_config32(dev, 0xc8, dword);
-#endif
-
- if (chip_rev == 0x11) {
- /* [18] Clock Gate Enable = 1 */
- dword = pci_read_config32(dev, 0xf0);
- dword |= 0x00040008;
- pci_write_config32(dev, 0xf0, dword);
- }
-
- }
- return;
-}
-
-#define BRIDGE_40_BIT_SUPPORT 0
-#if BRIDGE_40_BIT_SUPPORT
-static void bridge_read_resources(struct device *dev)
-{
- struct resource *res;
- pci_bus_read_resources(dev);
- res = find_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- res->limit = 0xffffffffffULL;
- }
-}
-
-static void bridge_set_resources(struct device *dev)
-{
- struct resource *res;
- res = find_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- resource_t base, end;
- /* set the memory range */
- dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- res->flags |= IORESOURCE_STORED;
- base = res->base;
- end = resource_end(res);
- pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
- pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
- pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
- pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
-
- report_resource_stored(dev, res, "");
- }
- pci_dev_set_resources(dev);
-}
-#endif /* BRIDGE_40_BIT_SUPPORT */
-
-static struct device_operations pcix_ops = {
-#if BRIDGE_40_BIT_SUPPORT
- .read_resources = bridge_read_resources,
- .set_resources = bridge_set_resources,
-#else
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
-#endif
- .enable_resources = pci_bus_enable_resources,
- .init = amd8132_pcix_init,
- .scan_bus = amd8132_scan_bridge,
- .reset_bus = pci_bus_reset,
-};
-
-static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7458,
-};
-
-static void ioapic_enable(device_t dev)
-{
- uint32_t value;
-
- value = pci_read_config32(dev, 0x44);
- if (dev->enabled) {
- value |= ((1 << 1) | (1 << 0));
- } else {
- value &= ~((1 << 1) | (1 << 0));
- }
- pci_write_config32(dev, 0x44, value);
-}
-static void amd8132_ioapic_init(device_t dev)
-{
- uint32_t dword;
- unsigned chip_rev;
-
- /* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
-
- if (chip_rev == 0x01) {
-#if 0
- /* Errata #43 */
- dword = pci_read_config32(dev, 0xc8);
- dword |= (0x3<<23);
- pci_write_config32(dev, 0xc8, dword);
-#endif
-
- }
-
-
- if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
- //for b1 b2
- /* Errata #73 */
- dword = pci_read_config32(dev, 0x80);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x80, dword);
- dword = pci_read_config32(dev, 0x88);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x88, dword);
-
- /* Errata #74 */
- dword = pci_read_config32(dev, 0x7c);
- dword &= ~(0x3<<30);
- dword |= (0x01<<30);
- pci_write_config32(dev, 0x7c, dword);
- }
-
-}
-
-static struct pci_operations pci_ops_pci_dev = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-static struct device_operations ioapic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = amd8132_ioapic_init,
- .scan_bus = 0,
- .enable = ioapic_enable,
- .ops_pci = &pci_ops_pci_dev,
-};
-
-static const struct pci_driver ioapic_driver __pci_driver = {
- .ops = &ioapic_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7459,
-
-};
+/* Nothing here yet */
===================================================================
@@ -1,129 +1,24 @@
-/* Copyright 2005 AMD
- * 2005.08 yhlu add microcode support
- */
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-//@DOC
-// in model_fxx_update_microcode.c
/*
-$1.0$
-*/
-// Description: microcode patch support for k8
-// by yhlu
-//
-//============================================================================
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-
-#include <cpu/amd/microcode.h>
-
-static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
-
-#if CONFIG_K8_REV_F_SUPPORT == 0
- #include "microcode_rev_c.h"
- #include "microcode_rev_d.h"
- #include "microcode_rev_e.h"
-#endif
-
-#if CONFIG_K8_REV_F_SUPPORT == 1
-// #include "microcode_rev_f.h"
-#endif
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
-
-static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
- static unsigned id_mapping_table[] = {
- #if CONFIG_K8_REV_F_SUPPORT == 0
- 0x0f48, 0x0048,
- 0x0f58, 0x0048,
-
- 0x0f4a, 0x004a,
- 0x0f5a, 0x004a,
- 0x0f7a, 0x004a,
- 0x0f82, 0x004a,
- 0x0fc0, 0x004a,
- 0x0ff0, 0x004a,
-
- 0x10f50, 0x0150,
- 0x10f70, 0x0150,
- 0x10f80, 0x0150,
- 0x10fc0, 0x0150,
- 0x10ff0, 0x0150,
-
- 0x20f10, 0x0210,
- 0x20f12, 0x0210,
- 0x20f32, 0x0210,
- 0x20fb1, 0x0210,
- #endif
-
- #if CONFIG_K8_REV_F_SUPPORT == 1
-
- #endif
-
- };
-
-
- unsigned new_id;
- int i;
-
- new_id = 0;
-
- for(i=0; i<sizeof(id_mapping_table); i+=2 ) {
- if(id_mapping_table[i]==orig_id) {
- new_id = id_mapping_table[i+1];
- break;
- }
- }
-
- return new_id;
-
-}
-
void model_fxx_update_microcode(unsigned cpu_deviceid)
{
- unsigned equivalent_processor_rev_id;
-
- /* Update the microcode */
- equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
- if(equivalent_processor_rev_id != 0)
- amd_update_microcode(microcode_updates, equivalent_processor_rev_id);
-
+ /* Nothing here yet */
}
===================================================================
@@ -1,316 +1,52 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-
/*
- * 2005.9 yhlu add madt lapic creat dynamically and SRAT related
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <string.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
-#include <device/pci.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdk8_sysconf.h>
#include "amdk8_acpi.h"
-//it seems some functions can be moved arch/i386/boot/acpi.c
-
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
- cpu_index++;
- }
return current;
}
unsigned long acpi_create_srat_lapics(unsigned long current)
{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- cpu_index++;
- }
- return current;
+ return current
}
-static unsigned long resk(uint64_t value)
-{
- unsigned long resultk;
- if (value < (1ULL << 42)) {
- resultk = value >> 10;
- } else {
- resultk = 0xffffffff;
- }
- return resultk;
-}
-
-struct acpi_srat_mem_state {
- unsigned long current;
-};
-
-static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
-{
- struct acpi_srat_mem_state *state = gp;
- unsigned long basek, sizek;
- basek = resk(res->base);
- sizek = resk(res->size);
-
- printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
- dev_path(dev), res->index, basek, sizek);
- /*
- * 0-640K must be on node 0
- * next range is from 1M---
- * So will cut off before 1M in the mem range
- */
- if((basek+sizek)<1024) return;
-
- if(basek<1024) {
- sizek -= 1024 - basek;
- basek = 1024;
- }
-
- // need to figure out NV
- state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
-}
-
unsigned long acpi_fill_srat(unsigned long current)
{
- struct acpi_srat_mem_state srat_mem_state;
-
- /* create all subtables for processors */
- current = acpi_create_srat_lapics(current);
-
- /* create all subteble for memory range */
-
- /* 0-640K must be on node 0 */
- current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
-
- srat_mem_state.current = current;
- search_global_resources(
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- set_srat_mem, &srat_mem_state);
-
- current = srat_mem_state.current;
return current;
}
unsigned long acpi_fill_slit(unsigned long current)
{
- /* need to find out the node num at first */
- /* fill the first 8 byte with that num */
- /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
-
- /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */
- static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4,
- 1, 0, 2, 1, 3, 2, 4, 3,
- 1, 2, 0, 1, 1, 2, 2, 3,
- 2, 1, 1, 0, 2, 1, 3, 2,
- 2, 3, 1, 2, 0, 1, 1, 2,
- 3, 2, 2, 1, 1, 0, 2, 1,
- 3, 4, 2, 3, 1, 2, 0, 1,
- 4, 4, 3, 2, 2, 1, 1, 0 };
-
-// u8 outer_node[8];
-
- u8 *p = (u8 *)current;
- int nodes = sysconf.nodes;
- int i,j;
- memset(p, 0, 8+nodes*nodes);
-// memset((u8 *)outer_node, 0, 8);
- *p = (u8) nodes;
- p += 8;
-
-#if 0
- for(i=0;i<sysconf.hc_possible_num;i++) {
- if((sysconf.pci1234[i]&1) !=1 ) continue;
- outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
- }
-#endif
-
- for(i=0;i<nodes;i++) {
- for(j=0;j<nodes; j++) {
- if(i==j) {
- p[i*nodes+j] = 10;
- } else {
-#if 0
- int k;
- u8 latency_factor = 0;
- int k_start, k_end;
- if(i<j) {
- k_start = i;
- k_end = j;
- } else {
- k_start = j;
- k_end = i;
- }
- for(k=k_start;k<=k_end; k++) {
- if(outer_node[k]) {
- latency_factor = 1;
- break;
- }
- }
- p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
-#else
- p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
-#endif
-
- }
- }
- }
-
- current += 8+nodes*nodes;
-
return current;
}
-static int k8acpi_write_HT(void) {
- int len, lenp, i;
-
- len = acpigen_write_name("HCLK");
- lenp = acpigen_write_package(HC_POSSIBLE_NUM);
-
- for(i=0;i<sysconf.hc_possible_num;i++) {
- lenp += acpigen_write_dword(sysconf.pci1234[i]);
- }
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- lenp += acpigen_write_dword(0x0);
- }
-
- acpigen_patch_len(lenp - 1);
- len += lenp;
-
- len += acpigen_write_name("HCDN");
- lenp = acpigen_write_package(HC_POSSIBLE_NUM);
-
- for(i=0;i<sysconf.hc_possible_num;i++) {
- lenp += acpigen_write_dword(sysconf.hcdn[i]);
- }
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- lenp += acpigen_write_dword(0x20202020);
- }
- acpigen_patch_len(lenp - 1);
- len += lenp;
-
- return len;
-}
-
-static int k8acpi_write_pci_data(int dlen, const char *name, int offset) {
- device_t dev;
- uint32_t dword;
- int len, lenp, i;
-
- dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-
- len = acpigen_write_name(name);
- lenp = acpigen_write_package(dlen);
- for(i=0; i<dlen; i++) {
- dword = pci_read_config32(dev, offset+i*4);
- lenp += acpigen_write_dword(dword);
- }
- // minus the opcode
- acpigen_patch_len(lenp - 1);
- return len + lenp;
-}
-
int k8acpi_write_vars(void)
{
- int lens;
- msr_t msr;
- char pscope[] = "\\_SB.PCI0";
-
- lens = acpigen_write_scope(pscope);
- lens += k8acpi_write_pci_data(4, "BUSN", 0xe0);
- lens += k8acpi_write_pci_data(8, "PCIO", 0xc0);
- lens += k8acpi_write_pci_data(16, "MMIO", 0x80);
- lens += acpigen_write_name_byte("SBLK", sysconf.sblk);
- lens += acpigen_write_name_byte("CBST",
- ((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0);
- lens += acpigen_write_name_dword("SBDN", sysconf.sbdn);
- msr = rdmsr(TOP_MEM);
- lens += acpigen_write_name_dword("TOM1", msr.lo);
- msr = rdmsr(TOP_MEM2);
- lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo);
-
- lens += k8acpi_write_HT();
- //minus opcode
- acpigen_patch_len(lens - 1);
- return lens;
+ return 0;
}
void update_ssdtx(void *ssdtx, int i)
{
- u8 *PCI;
- u8 *HCIN;
- u8 *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i < 7) {
- *PCI = (u8) ('4' + i - 1);
- } else {
- *PCI = (u8) ('A' + i - 1 - 6);
- }
- *HCIN = (u8) i;
- *UID = (u8) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
}