Patchwork Support for HP DL165 G6

login
register
about
Submitter Arne Georg Gleditsch
Date 2010-05-26 17:03:52
Message ID <4BFD5478.2090306@numascale.com>
Download mbox | patch
Permalink /patch/1396/
State Accepted
Commit r1065
Headers show

Comments

Arne Georg Gleditsch - 2010-05-26 17:03:52
On 26. mai 2010 16:18, Michael Karcher wrote:
> Maybe because we preferrably choose chips with subsystem IDs. Maybe
> because someone thought that a new board revision very probably contains
> a more modern graphics chip. In this case, you are very right in
> suggesting to take the network chip as secondary PCI ID. You need to
> find out what subsystem IDs are used (if any) in the DL145 and the
> DL165.
> 
> If you send
>  - lspci -vvvxxxnn, superiotool -deV and flashrom -V output of your
> DL165 (general requirement for having new boards added),
>  - an updated patch that uses the network instead of the graphics chip
> for both boards, including a sign-off[1],
>  - preferably at least PCI ID info including subsystems for the DL145,

According to
http://merlin.ugent.be/~samuel/dl145g3/info/lspci-vnn.txt, the DL145 is
equipped thus:

08:04.0 Ethernet controller [0200]: Broadcom Corporation NetXtreme BCM5715 Gigabit Ethernet [14e4:1678] (rev a3)
	Subsystem: Hewlett-Packard Company NC326i PCIe Dual Port Gigabit Server Adapter [103c:703e]

Full lspci listing and superio and flashrom output for the DL165 follows,
as well as updated patch.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Arne Georg Gleditsch - 2010-06-03 07:47:20
On 26. mai 2010 19:03, Arne Georg Gleditsch wrote:
> Full lspci listing and superio and flashrom output for the DL165 follows,
> as well as updated patch.

Any takers?

Patch

Index: board_enable.c
===================================================================
--- board_enable.c	(revision 1013)
+++ board_enable.c	(working copy)
@@ -518,6 +518,15 @@ 
 	return 0;
 }
 
+static int board_hp_dl165_g6_enable(const char *name)
+{
+	/* Variant of DL145, with slightly different pin placement. */
+	sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
+	sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
+
+	return 0;
+}
+
 static int board_ibm_x3455(const char *name)
 {
 	/* raise gpio13 */
@@ -1434,7 +1443,8 @@ 
 	{0x1106, 0x0686, 0x1106, 0x0686,  0x1106, 0x3058, 0x1458, 0xa000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-7ZM",                512, OK, NULL},
 	{0x1106, 0x3227, 0x1458, 0x5001,  0x10ec, 0x8139, 0x1458, 0xe000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-7VT600",             0,   OK, it8705f_write_enable_2e},
 	{0x10DE, 0x0050, 0x1458, 0x0C11,  0x10DE, 0x005e, 0x1458, 0x5000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-K8N-SLI",            0,   OK, nvidia_mcp_gpio21_raise},
-	{0x1166, 0x0223, 0x103c, 0x320d,  0x102b, 0x0522, 0x103c, 0x31fa, NULL,          "hp",         "dl145_g3",    "HP",          "DL145 G3",              0,   OK, board_hp_dl145_g3_enable},
+	{0x1166, 0x0223, 0x103c, 0x320d,  0x14e4, 0x1678, 0x103c, 0x703e, NULL,          "hp",         "dl145_g3",    "HP",          "DL145 G3",              0,   OK, board_hp_dl145_g3_enable},
+	{0x1166, 0x0223, 0x103c, 0x320d,  0x14e4, 0x1648, 0x103c, 0x310f, NULL,          "hp",         "dl165_g6",    "HP",          "DL165 G6",              0,   OK, board_hp_dl165_g6_enable},
 	{0x8086, 0x2415, 0x103c, 0x1249,  0x10b7, 0x9200, 0x103c, 0x1246, NULL,          NULL,         NULL,          "HP",          "Vectra VL400",          0,   OK, board_hp_vl400}, 
 	{0x8086, 0x1a30, 0x103c, 0x1a30,  0x8086, 0x2443, 0x103c, 0x2440, "^VL420$",     NULL,         NULL,          "HP",          "VL420 SFF",             0,   OK, intel_ich_gpio22_raise},
 	{0x8086, 0x27A0,      0,      0,  0x8086, 0x27B9,      0,      0, NULL,          "ibase",      "mb899",       "iBASE",       "MB899",                 0,   NT, intel_ich_gpio26_raise},