Patchwork Nokia IP530 finally fully working

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Submitter marc bertens
Date 2010-05-31 20:08:18
Message ID <1275336498.6402.32.camel@andrala.reboot>
Download mbox | patch
Permalink /patch/1433/
State Accepted
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marc bertens - 2010-05-31 20:08:18
hi all,

This is the final patch for the Nokia IP530.

Patch

Index: src/mainboard/nokia/ip530/Kconfig
===================================================================
--- src/mainboard/nokia/ip530/Kconfig	(revision 5600)
+++ src/mainboard/nokia/ip530/Kconfig	(working copy)
@@ -25,9 +25,9 @@ 
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_SMSC_SMSCSUPERIO
 	select ROMCC
-	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select GENERATE_PIRQ_TABLE
 	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
 	string
@@ -46,6 +46,6 @@ 
 
 config IRQ_SLOT_COUNT
 	int
-	default 6
+	default 22
 	depends on BOARD_NOKIA_IP530
 
Index: src/mainboard/nokia/ip530/devicetree.cb
===================================================================
--- src/mainboard/nokia/ip530/devicetree.cb	(revision 5600)
+++ src/mainboard/nokia/ip530/devicetree.cb	(working copy)
@@ -1,5 +1,6 @@ 
 ##
 ## This file is part of the coreboot project.
+## This is the device tree for a Nokia IP530.
 ##
 ## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
 ##
@@ -17,78 +18,56 @@ 
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
-
-chip northbridge/intel/i440bx		# Northbridge
-  device lapic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# CPU
-      device lapic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/smsc/smscsuperio	# Super I/O (SMSC FDC37C878)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 3f0.4 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.7 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.9 on		# Game port
-            io 0x60 = 0x201
-          end
-          device pnp 3f0.a on		# Power-management events (PME)
-            io 0x60 = 0x600
-          end
-          device pnp 3f0.b on		# MIDI port (MPU-401)
-            io 0x60 = 0x330
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 7.1 on end		# IDE
-      device pci 7.2 on end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-    device pci 0d.0 on end		# NIC (DEC DECchip 21142/43)
-    device pci 0e.0 on end		# NIC (DEC DECchip 21142/43)
-    device pci 0f.0 on end		# CardBus bridge (TI PCI1225)
-    device pci 0f.1 on end		# CardBus bridge (TI PCI1225)
-  end
-  device pci_domain 1 on		# PCI domain 1
-    device pci 00.0 on end		# PCI bridge (DEC DECchip 21150)
-  end
-  device pci_domain 2 on		# PCI domain 2
-    device pci 04.0 on end		# NIC (DECchip 21142/43)
-    device pci 04.0 on end		# NIC (DECchip 21142/43)
-  end
+chip northbridge/intel/i440bx						# Northbridge
+	device lapic_cluster 0 on					# APIC cluster
+		chip cpu/intel/socket_PGA370				# CPU
+			device lapic 0 on end				# APIC
+		end
+	end
+	device pci_domain 0 on						# PCI domain
+		device pci 0.0 on end					# Host bridge
+		device pci 1.0 on end					# PCI/AGP bridge
+		chip southbridge/intel/i82371eb				# Southbridge
+			device pci 7.0 on				# ISA bridge
+				chip superio/smsc/smscsuperio		# Super I/O FDC 37C878
+					# There is no connector for the Floppy
+					# is on the board the FDD controller is
+					# disabled.
+					device pnp 3f0.0 off end	# Floppy
+					# There is no connector for the LPT
+					# device is on the board the LPT
+					# controller is disabled.
+					device pnp 3f0.3 off end	# Parallel port
+					device pnp 3f0.4 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 3f0.5 on		# COM2 / IR
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 3f0.7 on end		# PS/2 keyboard / mouse
+					device pnp 3f0.6 on end		# RTC
+					device pnp 3f0.8 on end		# AUX I/O
+					# There is no ACPI support for this
+					# board, therefor its disabled.
+					device pnp 3f0.A off end	# ACPI
+				end
+			end
+			device pci 7.1 on end		# IDE
+			# There is no USB connector therefor its disabled
+			device pci 7.2 off end		# USB
+			# There is no ACPI support for this board
+			# so ACPI is disabled.
+			device pci 7.3 off end		# ACPI
+			register "ide0_enable" = "1"
+			register "ide1_enable" = "1"
+			register "ide_legacy_enable" = "1"
+			# Enable UDMA/33 for higher speed if your IDE device(s) support it.
+			register "ide0_drive0_udma33_enable" = "1"
+			register "ide0_drive1_udma33_enable" = "1"
+			register "ide1_drive0_udma33_enable" = "1"
+			register "ide1_drive1_udma33_enable" = "1"
+		end
+	end
 end
-
Index: src/mainboard/nokia/ip530/irq_tables.c
===================================================================
--- src/mainboard/nokia/ip530/irq_tables.c	(revision 5600)
+++ src/mainboard/nokia/ip530/irq_tables.c	(working copy)
@@ -31,15 +31,46 @@ 
 	0x122e,			/* Device */
 	0,			/* Miniport */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x36,			/* Checksum */
+	0x44,			/* Checksum */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
-		{0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
-		{0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
-		{0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+		/**
+		 *	Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
+		 */
+		// Southbridge 82371
+		{ 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+		// On-board PCI-to-PCI bridge
+		{ 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+		// ETH1 on front panel
+		{ 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+		// ETH2 on front panel
+		{ 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+		// ETH3 on front panel
+		{ 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+		// ETH4 on front panel
+		{ 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+		// PCMCIA/Cardbus controller
+		{ 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+		// Bridge for slot 1 (top)
+		{ 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
+		// PCI compact slots 1 (top)
+		{ 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
+		{ 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
+		{ 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
+		{ 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
+		// Bridge for slot 2 (middle)
+		{ 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+		// PCI compact slots 2 (middle)
+		{ 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
+		{ 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
+		{ 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
+		{ 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
+		// Bridge for slot 3 (bottom)
+		{ 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+		// PCI compact slots 3 (bottom)
+		{ 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
+		{ 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
+		{ 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
+		{ 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
 	}
 };
 
@@ -47,3 +78,13 @@ 
 {
 	return copy_pirq_routing_table(addr);
 }
+
+/**
+ * TODO: This stub function is here until the point is solved in the
+ * main code of coreboot. see also arch/i386/boot/pirq_tables.c
+ */
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+	return;
+}
+
Index: src/mainboard/nokia/ip530/mainboard.c
===================================================================
--- src/mainboard/nokia/ip530/mainboard.c	(revision 5600)
+++ src/mainboard/nokia/ip530/mainboard.c	(working copy)
@@ -20,7 +20,44 @@ 
 
 #include <device/device.h>
 #include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#define OUTB	outb
+#define INB		inb
 
+/*
+*	Taken from flashrom project
+*	Generic Super I/O helper functions
+*/
+static uint8_t sio_read(uint16_t port, uint8_t reg)
+{
+	OUTB( reg, port );
+	return ( INB( port + 1 ) );
+}
+
+static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
+{
+	OUTB( reg, port );
+	OUTB( data, port + 1 );
+	return;
+}
+
+static void nokia_ip530_board_enable( device_t dev )
+{
+	print_debug( "Setting up IP530-Super I/O devices\n");
+	sio_write( 0x20, 0x03, 0x80 );
+	printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
+	sio_write( 0x20, 0x22, 0x30 );
+	printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
+	sio_write( 0x20, 0x24, 0x84 );
+	printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
+	return;
+}
+
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("Nokia IP530 Mainboard")
+	CHIP_NAME("NOKIA IP530 Mainboard")
+	.enable_dev = nokia_ip530_board_enable,
 };