Patchwork various things to aid with CBFS on PPC, plus...

login
register
about
Submitter Patrick Georgi
Date 2009-08-19 21:08:07
Message ID <4A8C69B7.3030403@georgi-clan.de>
Download mbox | patch
Permalink /patch/146/
State Accepted
Headers show

Comments

Patrick Georgi - 2009-08-19 21:08:07
Hi,

20090819-2-trim-down-cbfs:
CBFS uses sprintf, which requires vtxprintf, which requires (in the 
current design) a nested function. That works on x86, but on PPC this 
requires a trampoline. In the ROM stage, this is not available, so 
remove the single use of sprintf and replace it with a direct string 
handler - it's only used to fill in fixed-length hex values.

20090819-3-more-noreturns-in-romcc:
Mark two more functions in romcc as noreturn. Helps clang's scan-build a bit

20090819-4-cbfsify-ppc:
Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and 
not complete yet.

20090819-5-fix-ppc-build:
The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat 
plausible value.


All of them are
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

Index: util/romcc/romcc.c
===================================================================
--- util/romcc/romcc.c	(revision 4557)
+++ util/romcc/romcc.c	(working copy)
@@ -1768,7 +1768,7 @@
 		state->file->report_name, state->file->report_line, col);
 }
 
-static void internal_error(struct compile_state *state, struct triple *ptr, 
+static void __attribute__ ((noreturn)) internal_error(struct compile_state *state, struct triple *ptr, 
 	const char *fmt, ...)
 {
 	FILE *fp = state->errout;
@@ -1806,7 +1806,7 @@
 
 
 
-static void error(struct compile_state *state, struct triple *ptr, 
+static void __attribute__ ((noreturn)) error(struct compile_state *state, struct triple *ptr, 
 	const char *fmt, ...)
 {
 	FILE *fp = state->errout;
Index: src/arch/ppc/Config.lb
===================================================================
--- src/arch/ppc/Config.lb	(revision 4557)
+++ src/arch/ppc/Config.lb	(working copy)
@@ -1,3 +1,4 @@
+uses CONFIG_CBFS
 ldscript init/ldscript.lb
 
 makerule coreboot.strip 
@@ -10,6 +11,11 @@
 	action "cp $< $@"
 end
 
+if CONFIG_CBFS
+	initobject /src/lib/cbfs.o
+	initobject /src/lib/lzma.o
+end
+
 dir init
 dir lib
 dir boot
Index: src/arch/ppc/init/ppc_main.c
===================================================================
--- src/arch/ppc/init/ppc_main.c	(revision 4557)
+++ src/arch/ppc/init/ppc_main.c	(working copy)
@@ -5,13 +5,8 @@
 
 #include <board.h>
 #include <sdram.h>
+#include <cbfs.h>
 
-extern unsigned _iseg[];
-extern unsigned _liseg[];
-extern unsigned _eliseg[];
-
-void (*payload)(void) = (void (*)(void))_iseg;
-
 /*
  * At this point we're running out of flash with our
  * stack in cache ram. We need to do the following:
@@ -25,8 +20,7 @@
 
 void ppc_main(void)
 {
-	unsigned *from;
-	unsigned *to;
+	void (*payload)(void);
 
 	/*
  	 * very early board initialization
@@ -49,15 +43,9 @@
 	flush_dcache();
 
 	/*
-	 * Relocate payload (text & data) if necessary
+	 * Relocate payload (text & data)
 	 */
-	if (_liseg != _iseg) {	
-		from = _liseg;
-		to = _iseg;
-		while (from < _eliseg)
-			*to++ = *from++;
-	}
-
+	payload = cbfs_load_stage("fallback/coreboot_ram");
 	payload();
 
 	/* NOT REACHED */
Index: util/cbfstool/tools/cbfs-mkstage.c
===================================================================
--- util/cbfstool/tools/cbfs-mkstage.c	(revision 4557)
+++ util/cbfstool/tools/cbfs-mkstage.c	(working copy)
@@ -29,6 +29,18 @@
 #include "common.h"
 #include "../cbfs.h"
 
+unsigned int idemp(unsigned int x)
+{
+	return x;
+}
+
+unsigned int swap32(unsigned int x)
+{
+	return ((x>>24) | ((x>>8) & 0xff00) | ((x<<8) & 0xff0000) | (x<<24));
+}
+
+unsigned int (*elf32_to_native)(unsigned int)=idemp;
+
 int parse_elf(unsigned char *input, unsigned char **output,
 	      int mode, void (*compress) (char *, int, char *, int *))
 {
@@ -42,10 +54,22 @@
 	struct cbfs_stage *stage;
 	unsigned int data_start, data_end, mem_end;
 
+	int elf_bigendian = 0;
+	int host_bigendian = 0;
+	if (ehdr->e_ident[EI_DATA]==ELFDATA2MSB) {
+		elf_bigendian = 1;
+	}
+	if ((unsigned int)"1234"==0x31323334) {
+		host_bigendian = 1;
+	}
+	if (elf_bigendian != host_bigendian) {
+		elf32_to_native = swap32;
+	}
+
 	headers = ehdr->e_phnum;
 	header = (char *)ehdr;
 
-	phdr = (Elf32_Phdr *) & (header[ehdr->e_phoff]);
+	phdr = (Elf32_Phdr *) & header[elf32_to_native(ehdr->e_phoff)];
 
 	/* Now, regular headers - we only care about PT_LOAD headers,
 	 * because thats what we're actually going to load
@@ -58,19 +82,19 @@
 	for (i = 0; i < headers; i++) {
 		unsigned int start, mend, rend;
 
-		if (phdr[i].p_type != PT_LOAD)
+		if (elf32_to_native(phdr[i].p_type) != PT_LOAD)
 			continue;
 
 		/* Empty segments are never interesting */
-		if (phdr[i].p_memsz == 0)
+		if (elf32_to_native(phdr[i].p_memsz) == 0)
 			continue;
 
 		/* BSS */
 
-		start = phdr[i].p_paddr;
+		start = elf32_to_native(phdr[i].p_paddr);
 
-		mend = start + phdr[i].p_memsz;
-		rend = start + phdr[i].p_filesz;
+		mend = start + elf32_to_native(phdr[i].p_memsz);
+		rend = start + elf32_to_native(phdr[i].p_filesz);
 
 		if (start < data_start)
 			data_start = start;
@@ -94,14 +118,14 @@
 
 	for (i = 0; i < headers; i++) {
 
-		if (phdr[i].p_type != PT_LOAD)
+		if (elf32_to_native(phdr[i].p_type) != PT_LOAD)
 			continue;
 
-		if (phdr[i].p_memsz == 0)
+		if (elf32_to_native(phdr[i].p_memsz) == 0)
 			continue;
 
-		memcpy(buffer + (phdr[i].p_paddr - data_start),
-		       &header[phdr[i].p_offset], phdr[i].p_filesz);
+		memcpy(buffer + (elf32_to_native(phdr[i].p_paddr) - data_start),
+		       &header[elf32_to_native(phdr[i].p_offset)], elf32_to_native(phdr[i].p_filesz));
 	}
 
 	/* Now make the output buffer */
Index: src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
===================================================================
--- src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	(revision 4557)
+++ src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	(working copy)
@@ -94,8 +94,8 @@
 default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
 # coreboot must fit into 128KB
-default CONFIG_ROM_IMAGE_SIZE=131072
-default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
+default CONFIG_ROM_IMAGE_SIZE=160*1024
+default CONFIG_ROM_SIZE=384*1024
 default CONFIG_PAYLOAD_SIZE=262144
 
 # Set stack and heap sizes (stage 2)
Index: src/mainboard/totalimpact/briq/Options.lb
===================================================================
--- src/mainboard/totalimpact/briq/Options.lb	(revision 4557)
+++ src/mainboard/totalimpact/briq/Options.lb	(working copy)
@@ -96,6 +96,7 @@
 
 # ROM is 1Mb
 default CONFIG_ROM_SIZE=1048576
+default CONFIG_ROM_IMAGE_SIZE=128*1024
 
 # Set stack and heap sizes (stage 2)
 default CONFIG_STACK_SIZE=0x10000
Index: src/mainboard/embeddedplanet/ep405pc/Options.lb
===================================================================
--- src/mainboard/embeddedplanet/ep405pc/Options.lb	(revision 4557)
+++ src/mainboard/embeddedplanet/ep405pc/Options.lb	(working copy)
@@ -106,6 +106,7 @@
 default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
 
 default CONFIG_ROM_SIZE=1048576
+default CONFIG_ROM_IMAGE_SIZE=160*1024
 
 ## Board has fixed size RAM
 default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
Myles Watson - 2009-08-19 21:29:01
> 20090819-2-trim-down-cbfs:


+static void tohex32(int val, char* dest)
+{
+	dest[0]=tohex8(val>>24);

Shouldn't val be unsigned?  You could also and this value with 0xff to
remove sign-extended bits.

> 20090819-3-more-noreturns-in-romcc:
> Mark two more functions in romcc as noreturn. Helps clang's scan-build a
> bit
> 
> 20090819-4-cbfsify-ppc:
> Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and
> not complete yet.
> 20090819-5-fix-ppc-build:
> The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat
> plausible value.
> 
> 
> All of them are
> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Stefan Reinauer - 2009-08-20 07:58:19
On 8/19/09 11:08 PM, Patrick Georgi wrote:
> +static int tohex8(int c)
> +{
> +	return (c<=9)?(c+'0'):(c-10+'a');
> +}
> +
> +static void tohex32(int val, char* dest)
> +{
> +	dest[0]=tohex8(val>>24);
> +	dest[1]=tohex8((val>>16) & 0xff);
> +	dest[2]=tohex8((val>>8) & 0xff);
> +	dest[3]=tohex8((val) & 0xff);
> +}
>   
I think I agree with Myles, those val/c should probably be u8 and u32?

Acked-by: Stefan Reinauer <stepan@coresystems.de>

Patch

Index: src/arch/i386/Config.lb
===================================================================
--- src/arch/i386/Config.lb	(revision 4557)
+++ src/arch/i386/Config.lb	(working copy)
@@ -13,7 +13,6 @@ 
 	if CONFIG_USE_FAILOVER_IMAGE
 	else
 		initobject /src/lib/cbfs.o
-		initobject /src/console/vsprintf.o
 		initobject /src/lib/lzma.o
 	end
 end
Index: src/lib/cbfs.c
===================================================================
--- src/lib/cbfs.c	(revision 4557)
+++ src/lib/cbfs.c	(working copy)
@@ -124,13 +124,27 @@ 
 	return (void *) CBFS_SUBHEADER(file);
 }
 
+static int tohex8(int c)
+{
+	return (c<=9)?(c+'0'):(c-10+'a');
+}
+
+static void tohex32(int val, char* dest)
+{
+	dest[0]=tohex8(val>>24);
+	dest[1]=tohex8((val>>16) & 0xff);
+	dest[2]=tohex8((val>>8) & 0xff);
+	dest[3]=tohex8((val) & 0xff);
+}
+
 void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest)
 {
-	char name[17];
+	char name[17]="pciXXXX,XXXX.rom";
 	struct cbfs_optionrom *orom;
 	u8 *src;
 
-	sprintf(name,"pci%04x,%04x.rom", vendor, device);
+	tohex32(vendor, name+3);
+	tohex32(device, name+8);
 
 	orom = (struct cbfs_optionrom *)
 		cbfs_find_file(name, CBFS_TYPE_OPTIONROM);