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Submitter Myles Watson
Date 2010-06-09 21:49:43
Message ID <AANLkTimrzWgxkmhq-xw6fnxP9Jofw5vvwdf2UMBjlv7Q@mail.gmail.com>
Download mbox | patch
Permalink /patch/1496/
State Accepted
Headers show

Comments

Myles Watson - 2010-06-09 21:49:43
On Wed, Jun 9, 2010 at 8:57 AM, Myles Watson <mylesgw@gmail.com> wrote:
> Same conversion as with resources from static arrays to lists, except
> there is no free list.
>
> Converting resource arrays to lists reduced the size of each device
> struct from 1092 to 228 bytes.
> Converting link arrays to lists reduced the size of each device struct
> from 228 to 68 bytes.
>
> fam10_pci.diff makes fam10 and k8 northbridge code a little more
> similar before the conversion.
>
> The next step for fam10 and k8 would be to reorganize the links so
> that the southbridge link is always first.  This would make some of
> the code a lot easier to follow.  Something to consider would be
> adding link numbers to the device tree, since that would allow the
> southbridge link to start in the correct place.
>

Signed-off-by: Myles Watson <mylesgw@gmail.com>

Removed some warnings and fixed static.c generation when the
southbridge link is not 0.

Thanks,
Myles
Stefan Reinauer - 2010-06-09 22:14:59
On 6/9/10 11:49 PM, Myles Watson wrote:
> Signed-off-by: Myles Watson <mylesgw@gmail.com>
>
> Removed some warnings and fixed static.c generation when the
> southbridge link is not 0.
>   
I didn't test this, but assuming we're not planning on getting rid of
malloc anymore, this is

Acked-by: Stefan Reinauer <stepan@coresystems.de>
Myles Watson - 2010-06-09 22:27:40
On Wed, Jun 9, 2010 at 4:14 PM, Stefan Reinauer <stepan@coresystems.de> wrote:
> On 6/9/10 11:49 PM, Myles Watson wrote:
>> Signed-off-by: Myles Watson <mylesgw@gmail.com>
>>
>> Removed some warnings and fixed static.c generation when the
>> southbridge link is not 0.
>>
> I didn't test this, but assuming we're not planning on getting rid of
> malloc anymore, this is

I'm willing to listen more before committing.  I remember you brought
up getting rid of malloc, but I don't see how you can get away from
it.  Are you suggesting a static global pool of resources and lists
that devices can use?  Am I totally missing your point?

Thanks,
Myles
Stefan Reinauer - 2010-06-09 22:32:29
On 6/10/10 12:27 AM, Myles Watson wrote:
> On Wed, Jun 9, 2010 at 4:14 PM, Stefan Reinauer <stepan@coresystems.de> wrote:
>   
>> On 6/9/10 11:49 PM, Myles Watson wrote:
>>     
>>> Signed-off-by: Myles Watson <mylesgw@gmail.com>
>>>
>>> Removed some warnings and fixed static.c generation when the
>>> southbridge link is not 0.
>>>
>>>       
>> I didn't test this, but assuming we're not planning on getting rid of
>> malloc anymore, this is
>>     
> I'm willing to listen more before committing.  I remember you brought
> up getting rid of malloc, but I don't see how you can get away from
> it.  Are you suggesting a static global pool of resources and lists
> that devices can use?  Am I totally missing your point?
>   
I believe it was easy when a device was just a fixed size huge array,
but the more dynamic this gets it becomes more complex.
We'd indeed need a fixed number of every "dynamic" data structure we
have. Which makes little sense when we're looking into making coreboot
use less memory and be more flexible. So I believe keeping malloc and
having 68byte sized devices is better than dropping malloc and having
1KB big devices.

Stefan
Myles Watson - 2010-06-09 22:42:39
On Wed, Jun 9, 2010 at 4:14 PM, Stefan Reinauer <stepan@coresystems.de> wrote:
> On 6/9/10 11:49 PM, Myles Watson wrote:
>> Signed-off-by: Myles Watson <mylesgw@gmail.com>
>>
>> Removed some warnings and fixed static.c generation when the
>> southbridge link is not 0.
>>
> I didn't test this, but assuming we're not planning on getting rid of
> malloc anymore, this is
>
> Acked-by: Stefan Reinauer <stepan@coresystems.de>
Rev 5626

Thanks,
Myles
ron minnich - 2010-06-10 00:19:30
getting rid of malloc was a beautiful theory that was killed by a
brutal gang of facts.

Don't you just hate it when that happens :-)

ron

Patch

Index: svn/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/amdfam10/northbridge.c
+++ svn/src/northbridge/amd/amdfam10/northbridge.c
@@ -55,6 +55,7 @@  static device_t __f0_dev[FX_DEVS];
 static device_t __f1_dev[FX_DEVS];
 static device_t __f2_dev[FX_DEVS];
 static device_t __f4_dev[FX_DEVS];
+static unsigned fx_devs=0;
 
 device_t get_node_pci(u32 nodeid, u32 fn)
 {
@@ -68,37 +69,37 @@  device_t get_node_pci(u32 nodeid, u32 fn
 #else
 	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
 #endif
-
 }
+
 static void get_fx_devs(void)
 {
 	int i;
-	if (__f1_dev[0]) {
-		return;
-	}
 	for(i = 0; i < FX_DEVS; i++) {
 		__f0_dev[i] = get_node_pci(i, 0);
 		__f1_dev[i] = get_node_pci(i, 1);
 		__f2_dev[i] = get_node_pci(i, 2);
 		__f4_dev[i] = get_node_pci(i, 4);
+		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+			fx_devs = i+1;
 	}
-	if (!__f1_dev[0]) {
-		printk(BIOS_ERR, "Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
-		die("Cannot go on\n");
+	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+		die("Cannot find 0:0x18.[0|1]\n");
 	}
 }
 
-static u32 f1_read_config32(u32 reg)
+static u32 f1_read_config32(unsigned reg)
 {
-	get_fx_devs();
+	if (fx_devs == 0)
+		get_fx_devs();
 	return pci_read_config32(__f1_dev[0], reg);
 }
 
-static void f1_write_config32(u32 reg, u32 value)
+static void f1_write_config32(unsigned reg, u32 value)
 {
 	int i;
-	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	if (fx_devs == 0)
+		get_fx_devs();
+	for(i = 0; i < fx_devs; i++) {
 		device_t dev;
 		dev = __f1_dev[i];
 		if (dev && dev->enabled) {
@@ -107,7 +108,6 @@  static void f1_write_config32(u32 reg, u
 	}
 }
 
-
 static u32 amdfam10_nodeid(device_t dev)
 {
 #if NODE_NUMS == 64
@@ -197,11 +197,10 @@  static u32 amdfam10_scan_chain(device_t 
 		 * We have no idea how many busses are behind this bridge yet,
 		 * so we set the subordinate bus number to 0xff for the moment.
 		 */
-
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 		// first chain will on bus 0
 		if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
-			 min_bus = max;
+			min_bus = max;
 		}
 	#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
 		// second chain will be on 0x40, third 0x80, forth 0xc0
@@ -211,12 +210,12 @@  static u32 amdfam10_scan_chain(device_t 
 			min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same
 		}
 		max = min_bus | (segn<<8);
-	 #else
+	#else
 		//other ...
 		else {
 			min_bus = ++max;
 		}
-	 #endif
+	#endif
 #else
 		min_bus = ++max;
 #endif
@@ -224,6 +223,7 @@  static u32 amdfam10_scan_chain(device_t 
 
 		dev->link[link].secondary = min_bus;
 		dev->link[link].subordinate = max_bus;
+
 		/* Read the existing primary/secondary/subordinate bus
 		 * number configuration.
 		 */
@@ -257,7 +257,6 @@  static u32 amdfam10_scan_chain(device_t 
 
 		max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
 
-
 		/* We know the number of busses behind this bridge.  Set the
 		 * subordinate bus number to it's real value
 		 */
@@ -270,7 +269,7 @@  static u32 amdfam10_scan_chain(device_t 
 		sysconf.ht_c_num++;
 
 		{
-		// config config_reg, and ht_unitid_base to update hcdn_reg;
+			// use ht_unitid_base to update hcdn_reg
 			u32 temp = 0;
 			for(i=0;i<4;i++) {
 				temp |= (ht_unitid_base[i] & 0xff) << (i*8);
@@ -279,23 +278,19 @@  static u32 amdfam10_scan_chain(device_t 
 			sysconf.hcdn_reg[ht_c_index] = temp;
 
 		}
-
-		store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf);
-
-
+	store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf);
 	return max;
 }
 
 static u32 amdfam10_scan_chains(device_t dev, u32 max)
 {
-	u32 nodeid;
+	unsigned nodeid;
 	u32 link;
-	u32 sblink = sysconf.sblk;
-	u32 offset_unitid = 0;
+	unsigned sblink = sysconf.sblk;
+	unsigned offset_unitid = 0;
 
 	nodeid = amdfam10_nodeid(dev);
 
-
 // Put sb chain in bus 0
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 	if(nodeid==0) {
@@ -306,12 +301,10 @@  static u32 amdfam10_scan_chains(device_t
 	}
 #endif
 
-
 #if CONFIG_PCI_BUS_SEGN_BITS
 	max = check_segn(dev, max, sysconf.nodes, &sysconf);
 #endif
 
-
 	for(link = 0; link < dev->links; link++) {
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 		if( (nodeid == 0) && (sblink == link) ) continue; //already done
@@ -330,14 +323,14 @@  static u32 amdfam10_scan_chains(device_t
 }
 
 
-static int reg_useable(u32 reg,device_t goal_dev, u32 goal_nodeid,
-			u32 goal_link)
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+			unsigned goal_link)
 {
 	struct resource *res;
-	u32 nodeid, link = 0;
+	unsigned nodeid, link = 0;
 	int result;
 	res = 0;
-	for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) {
+	for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
 		device_t dev;
 		dev = __f0_dev[nodeid];
 		if (!dev)
@@ -358,7 +351,7 @@  static int reg_useable(u32 reg,device_t 
 	return result;
 }
 
-static struct resource *amdfam10_find_iopair(device_t dev, u32 nodeid, u32 link)
+static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 {
 	struct resource *resource;
 	u32 free_reg, reg;
@@ -433,7 +426,7 @@  static void amdfam10_link_read_bases(dev
 	struct resource *resource;
 
 	/* Initialize the io space constraints on the current bus */
-	resource =  amdfam10_find_iopair(dev, nodeid, link);
+	resource = amdfam10_find_iopair(dev, nodeid, link);
 	if (resource) {
 		u32 align;
 #if CONFIG_EXT_CONF_SUPPORT == 1
@@ -454,12 +447,13 @@  static void amdfam10_link_read_bases(dev
 	/* Initialize the prefetchable memory constraints on the current bus */
 	resource = amdfam10_find_mempair(dev, nodeid, link);
 	if (resource) {
-		resource->base	= 0;
-		resource->size	= 0;
+		resource->base = 0;
+		resource->size = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran	= log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_BRIDGE;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+		resource->flags |= IORESOURCE_BRIDGE;
 
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
@@ -472,23 +466,20 @@  static void amdfam10_link_read_bases(dev
 	/* Initialize the memory constraints on the current bus */
 	resource = amdfam10_find_mempair(dev, nodeid, link);
 	if (resource) {
-		resource->base	= 0;
-		resource->size	= 0;
+		resource->base = 0;
+		resource->size = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran	= log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
 			normalize_resource(resource);
 		}
 #endif
-
 	}
 }
 
-
 static void amdfam10_read_resources(device_t dev)
 {
 	u32 nodeid, link;
@@ -501,7 +492,6 @@  static void amdfam10_read_resources(devi
 	}
 }
 
-
 static void amdfam10_set_resource(device_t dev, struct resource *resource,
 				u32 nodeid)
 {
@@ -613,7 +603,6 @@  static void amdfam10_set_resources(devic
 	}
 }
 
-
 static void amdfam10_enable_resources(device_t dev)
 {
 	pci_dev_enable_resources(dev);
@@ -665,14 +654,14 @@  static void amdfam10_domain_read_resourc
 			} else { // io
 				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
 			}
-			reg_link   = (limit >> 4) & 7;
+			reg_link = (limit >> 4) & 7;
 			reg_dev = __f0_dev[nodeid];
 			if (reg_dev) {
 				/* Reserve the resource  */
-				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
-				if (reg_resource) {
-					reg_resource->flags = 1;
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+				if (res) {
+					res->flags = 1;
 				}
 			}
 		}
@@ -714,8 +703,8 @@  static void ram_resource(device_t dev, u
 		return;
 	}
 	resource = new_resource(dev, index);
-	resource->base	= basek << 10;
-	resource->size	= sizek << 10;
+	resource->base = basek << 10;
+	resource->size = sizek << 10;
 	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
@@ -798,9 +787,9 @@  static struct hw_mem_hole_info get_hw_me
 // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
 // Does it make sense not to?
 #if CONFIG_AMDMCT == 0
-static void disable_hoist_memory(unsigned long hole_startk, int i)
+static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 {
-	int ii;
+	int i;
 	device_t dev;
 	struct dram_base_mask_t d;
 	u32 sel_m;
@@ -811,7 +800,7 @@  static void disable_hoist_memory(unsigne
 	u32 one_DCT;
 	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 	struct mem_info *meminfo;
-	meminfo = &sysinfox->meminfo[i];
+	meminfo = &sysinfox->meminfo[node_id];
 
 	one_DCT = get_one_DCT(meminfo);
 
@@ -824,54 +813,52 @@  static void disable_hoist_memory(unsigne
 
 	hole_sizek = (4*1024*1024) - hole_startk;
 
-	for(ii=NODE_NUMS-1;ii>i;ii--) {
+	for(i=NODE_NUMS-1;i>node_id;i--) {
 
-		d = get_dram_base_mask(ii);
+		d = get_dram_base_mask(i);
 
 		if(!(d.mask & 1)) continue;
 
 		d.base -= (hole_sizek>>9);
 		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(ii, d, sysconf.nodes);
+		set_dram_base_mask(i, d, sysconf.nodes);
 
-		if(get_DctSelHiEn(ii) & 1) {
-			sel_m = get_DctSelBaseAddr(ii);
+		if(get_DctSelHiEn(i) & 1) {
+			sel_m = get_DctSelBaseAddr(i);
 			sel_m -= hole_startk>>10;
-			set_DctSelBaseAddr(ii, sel_m);
+			set_DctSelBaseAddr(i, sel_m);
 		}
 	}
 
-	d = get_dram_base_mask(i);
-	dev = __f1_dev[i];
-	hoist = pci_read_config32(dev, 0xf0);
-	sel_hi_en = get_DctSelHiEn(i);
+	d = get_dram_base_mask(node_id);
+	dev = __f1_dev[node_id];
+	sel_hi_en = get_DctSelHiEn(node_id);
 
 	if(sel_hi_en & 1) {
-		sel_m = get_DctSelBaseAddr(i);
+		sel_m = get_DctSelBaseAddr(node_id);
 	}
-
+	hoist = pci_read_config32(dev, 0xf0);
 	if(hoist & 1) {
 		pci_write_config32(dev, 0xf0, 0);
 		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(i, d, sysconf.nodes);
+		set_dram_base_mask(node_id, d, sysconf.nodes);
 		if(one_DCT || (sel_m >= (hole_startk>>10))) {
 			if(sel_hi_en & 1) {
 				sel_m -= hole_startk>>10;
-				set_DctSelBaseAddr(i, sel_m);
+				set_DctSelBaseAddr(node_id, sel_m);
 			}
 		}
 		if(sel_hi_en & 1) {
-			set_DctSelBaseOffset(i, 0);
+			set_DctSelBaseOffset(node_id, 0);
 		}
-	}
-	else {
+	} else {
 		d.base -= (hole_sizek>>9);
 		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(i, d, sysconf.nodes);
+		set_dram_base_mask(node_id, d, sysconf.nodes);
 
 		if(sel_hi_en & 1) {
 			sel_m -= hole_startk>>10;
-			set_DctSelBaseAddr(i, sel_m);
+			set_DctSelBaseAddr(node_id, sel_m);
 		}
 	}
 
@@ -885,7 +872,7 @@  static void disable_hoist_memory(unsigne
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void amdfam10_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	struct resource *io, *mem1, *mem2;
@@ -902,7 +889,7 @@  static void pci_domain_set_resources(dev
 
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 
-	for(link=0; link<dev->links; link++) {
+	for(link = 0; link < dev->links; link++) {
 		/* Now reallocate the pci resources memory with the
 		 * highest addresses I can manage.
 		 */
@@ -946,16 +933,13 @@  static void pci_domain_set_resources(dev
 	for(res = &dev->resource_list; res; res = res->next)
 	{
 		res->flags |= IORESOURCE_ASSIGNED;
-		res->flags &= ~IORESOURCE_STORED;
-		link = (res>>2) & 3;
 		res->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, res, "");
-
 	}
 #endif
 
 	pci_tolm = 0xffffffffUL;
-	for(link=0;link<dev->links; link++) {
+	for(link = 0; link<dev->links; link++) {
 		pci_tolm = find_pci_tolm(&dev->link[link], pci_tolm);
 	}
 
@@ -967,7 +951,7 @@  static void pci_domain_set_resources(dev
 
 	// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
 	// MMIO hole. If you fix this here, please fix amdk8, too.
-	/* Round the mmio hold to 64M */
+	/* Round the mmio hole to 64M */
 	mmio_basek &= ~((64*1024) - 1);
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@@ -1057,11 +1041,11 @@  static void pci_domain_set_resources(dev
 					idx += 0x10;
 					sizek -= pre_sizek;
 #if CONFIG_WRITE_HIGH_TABLES==1
-					if (i==0 && high_tables_base==0) {
+					if (high_tables_base==0) {
 					/* Leave some space for ACPI, PIRQ and MP tables */
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk(BIOS_DEBUG, "(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1092,7 +1076,7 @@  static void pci_domain_set_resources(dev
 #if CONFIG_WRITE_HIGH_TABLES==1
 		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 			     i, mmio_basek, basek, limitk);
-		if (i==0 && high_tables_base==0) {
+		if (high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
 			high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
 			high_tables_size = HIGH_TABLES_SIZE * 1024;
@@ -1130,7 +1114,7 @@  static u32 amdfam10_domain_scan_bus(devi
 #endif
 
 
-	for(i=0;i<dev->links;i++) {
+	for(i = 0; i < dev->links; i++) {
 		max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
 	}
 
@@ -1138,7 +1122,7 @@  static u32 amdfam10_domain_scan_bus(devi
 	 * Including enabling relaxed ordering if it is safe.
 	 */
 	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < fx_devs; i++) {
 		device_t f0_dev;
 		f0_dev = __f0_dev[i];
 		if (f0_dev && f0_dev->enabled) {
@@ -1160,7 +1144,7 @@  static u32 amdfam10_domain_scan_bus(devi
 
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = amdfam10_domain_read_resources,
-	.set_resources	  = pci_domain_set_resources,
+	.set_resources	  = amdfam10_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,
 	.scan_bus	  = amdfam10_domain_scan_bus,
@@ -1208,11 +1192,9 @@  static void sysconf_init(device_t dev) /
 		} else {
 			sysconf.lift_bsp_apicid = 1;
 		}
-
 	}
 	#endif
 #endif
-
 }
 
 static u32 cpu_bus_scan(device_t dev, u32 max)
@@ -1243,11 +1225,7 @@  static u32 cpu_bus_scan(device_t dev, u3
 	get_option(&disable_siblings, "multi_core");
 #endif
 
-	// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it
-	//    still be 0)
-	// How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp???
-	//    and differ d0 and e0 single core
-
+	// How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
 	nb_cfg_54 = read_nb_cfg_54();
 
 #if CONFIG_CBB
@@ -1264,7 +1242,6 @@  static u32 cpu_bus_scan(device_t dev, u3
 			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
 		}
 		printk(BIOS_DEBUG, "\n");
-
 	}
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if(!dev_mc) {
@@ -1342,9 +1319,9 @@  static u32 cpu_bus_scan(device_t dev, u3
 				cdb_dev = pci_probe_dev(NULL, pbus,
 					PCI_DEVFN(devn, fn));
 			}
-			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
 		}
-		if(cdb_dev) {
+		if (cdb_dev) {
 			/* Ok, We need to set the links for that device.
 			 * otherwise the device under it will not be scanned
 			 */
@@ -1355,7 +1332,7 @@  static u32 cpu_bus_scan(device_t dev, u3
 #else
 			linknum = 4;
 #endif
-			if(cdb_dev->links < linknum) {
+			if (cdb_dev->links < linknum) {
 				for(link=cdb_dev->links; link<linknum; link++) {
 					 cdb_dev->link[link].link = link;
 					 cdb_dev->link[link].dev = cdb_dev;
@@ -1412,14 +1389,14 @@  static u32 cpu_bus_scan(device_t dev, u3
 				cpu->path.apic.node_id = i;
 				cpu->path.apic.core_id = j;
 	#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0)
-				 if(sysconf.enabled_apic_ext_id) {
+				if(sysconf.enabled_apic_ext_id) {
 					if(sysconf.lift_bsp_apicid) {
 						cpu->path.apic.apic_id += sysconf.apicid_offset;
 					} else
 					{
 						if (cpu->path.apic.apic_id != 0)
 							cpu->path.apic.apic_id += sysconf.apicid_offset;
-					 }
+					}
 				}
 	#endif
 				printk(BIOS_DEBUG, "CPU: %s %s\n",
@@ -1431,18 +1408,15 @@  static u32 cpu_bus_scan(device_t dev, u3
 	return max;
 }
 
-
 static void cpu_bus_init(device_t dev)
 {
 	initialize_cpus(&dev->link[0]);
 }
 
-
 static void cpu_bus_noop(device_t dev)
 {
 }
 
-
 static struct device_operations cpu_bus_ops = {
 	.read_resources	  = cpu_bus_noop,
 	.set_resources	  = cpu_bus_noop,
@@ -1451,7 +1425,6 @@  static struct device_operations cpu_bus_
 	.scan_bus	  = cpu_bus_scan,
 };
 
-
 static void root_complex_enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */
Index: svn/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/northbridge.c
+++ svn/src/northbridge/amd/amdk8/northbridge.c
@@ -55,17 +55,17 @@  static void get_fx_devs(void)
 	}
 }
 
-static uint32_t f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned reg)
 {
-	if ( fx_devs == 0)
+	if (fx_devs == 0)
 		get_fx_devs();
 	return pci_read_config32(__f1_dev[0], reg);
 }
 
-static void f1_write_config32(unsigned reg, uint32_t value)
+static void f1_write_config32(unsigned reg, u32 value)
 {
 	int i;
-	if ( fx_devs == 0)
+	if (fx_devs == 0)
 		get_fx_devs();
 	for(i = 0; i < fx_devs; i++) {
 		device_t dev;
@@ -76,22 +76,23 @@  static void f1_write_config32(unsigned r
 	}
 }
 
-static unsigned int amdk8_nodeid(device_t dev)
+static u32 amdk8_nodeid(device_t dev)
 {
 	return (dev->path.pci.devfn >> 3) - 0x18;
 }
 
-static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
+static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink,
+				u32 max, u32 offset_unitid)
 {
 
-		uint32_t link_type;
+		u32 link_type;
 		int i;
-		uint32_t busses, config_busses;
-		unsigned free_reg, config_reg;
-		unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
-		unsigned max_bus;
-		unsigned min_bus;
-		unsigned max_devfn;
+		u32 busses, config_busses;
+		u32 free_reg, config_reg;
+		u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
+		u32 max_bus;
+		u32 min_bus;
+		u32 max_devfn;
 
 		dev->link[link].cap = 0x80 + (link *0x20);
 		do {
@@ -111,7 +112,7 @@  static unsigned int amdk8_scan_chain(dev
 		 */
 		free_reg = 0;
 		for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
-			uint32_t config;
+			u32 config;
 			config = f1_read_config32(config_reg);
 			if (!free_reg && ((config & 3) == 0)) {
 				free_reg = config_reg;
@@ -150,7 +151,7 @@  static unsigned int amdk8_scan_chain(dev
 		max = min_bus;
 	#else
 		//other ...
-		else  {
+		else {
 			min_bus = ++max;
 		}
 	#endif
@@ -214,9 +215,9 @@  static unsigned int amdk8_scan_chain(dev
 		f1_write_config32(config_reg, config_busses);
 
 		{
-			// config config_reg, and ht_unitid_base to update hcdn_reg;
+			// use config_reg and ht_unitid_base to update hcdn_reg
 			int index;
-			unsigned temp = 0;
+			u32 temp = 0;
 			index = (config_reg-0xe0) >> 2;
 			for(i=0;i<4;i++) {
 				temp |= (ht_unitid_base[i] & 0xff) << (i*8);
@@ -225,16 +226,16 @@  static unsigned int amdk8_scan_chain(dev
 			sysconf.hcdn_reg[index] = temp;
 
 		}
-
 	return max;
 }
 
-static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
+static unsigned amdk8_scan_chains(device_t dev, unsigned max)
 {
 	unsigned nodeid;
 	unsigned link;
 	unsigned sblink = 0;
 	unsigned offset_unitid = 0;
+
 	nodeid = amdk8_nodeid(dev);
 
 	if(nodeid==0) {
@@ -247,7 +248,7 @@  static unsigned int amdk8_scan_chains(de
 #endif
 	}
 
-	for(link = 0; link < dev->links; link++) {
+	for (link = 0; link < dev->links; link++) {
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 		if( (nodeid == 0) && (sblink == link) ) continue; //already done
 #endif
@@ -261,16 +262,15 @@  static unsigned int amdk8_scan_chains(de
 
 		max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
 	}
-
 	return max;
 }
 
 
-static int reg_useable(unsigned reg,
-	device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+			unsigned goal_link)
 {
 	struct resource *res;
-	unsigned nodeid, link=0;
+	unsigned nodeid, link = 0;
 	int result;
 	res = 0;
 	for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -291,7 +291,6 @@  static int reg_useable(unsigned reg,
 			result = 1;
 		}
 	}
-
 	return result;
 }
 
@@ -351,10 +350,10 @@  static void amdk8_link_read_bases(device
 	/* Initialize the prefetchable memory constraints on the current bus */
 	resource = new_resource(dev, IOINDEX(2, link));
 	if (resource) {
-		resource->base  = 0;
-		resource->size  = 0;
+		resource->base = 0;
+		resource->size = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran  = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 		resource->flags |= IORESOURCE_BRIDGE;
@@ -363,10 +362,10 @@  static void amdk8_link_read_bases(device
 	/* Initialize the memory constraints on the current bus */
 	resource = new_resource(dev, IOINDEX(1, link));
 	if (resource) {
-		resource->base  = 0;
-		resource->size  = 0;
+		resource->base = 0;
+		resource->size = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran  = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
 	}
@@ -430,7 +429,7 @@  static void amdk8_set_resource(device_t 
 	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
-		uint32_t base, limit;
+		u32 base, limit;
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0xfe000fcc;
@@ -454,7 +453,7 @@  static void amdk8_set_resource(device_t 
 		f1_write_config32(reg, base);
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
-		uint32_t base, limit;
+		u32 base, limit;
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0x000000f0;
@@ -468,7 +467,7 @@  static void amdk8_set_resource(device_t 
 		f1_write_config32(reg, base);
 	}
 	resource->flags |= IORESOURCE_STORED;
-	sprintf(buf, " <node %d link %d>",
+	sprintf(buf, " <node %x link %x>",
 		nodeid, link);
 	report_resource_stored(dev, resource, buf);
 }
@@ -580,18 +579,18 @@  static void mcf0_control_init(struct dev
 }
 
 static struct device_operations northbridge_operations = {
-	.read_resources   = amdk8_read_resources,
-	.set_resources    = amdk8_set_resources,
+	.read_resources	  = amdk8_read_resources,
+	.set_resources	  = amdk8_set_resources,
 	.enable_resources = amdk8_enable_resources,
-	.init             = mcf0_control_init,
-	.scan_bus         = amdk8_scan_chains,
-	.enable           = 0,
-	.ops_pci          = 0,
+	.init		  = mcf0_control_init,
+	.scan_bus	  = amdk8_scan_chains,
+	.enable		  = 0,
+	.ops_pci	  = 0,
 };
 
 
 static const struct pci_driver mcf0_driver __pci_driver = {
-	.ops    = &northbridge_operations,
+	.ops	= &northbridge_operations,
 	.vendor = PCI_VENDOR_ID_AMD,
 	.device = 0x1100,
 };
@@ -608,20 +607,20 @@  static void amdk8_domain_read_resources(
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
 	for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
-		uint32_t base, limit;
+		u32 base, limit;
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x04);
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
-			unsigned nodeid, link;
+			unsigned nodeid, reg_link;
 			device_t reg_dev;
 			nodeid = limit & 7;
-			link   = (limit >> 4) & 3;
+			reg_link = (limit >> 4) & 3;
 			reg_dev = __f0_dev[nodeid];
 			if (reg_dev) {
 				/* Reserve the resource  */
 				struct resource *res;
-				res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
+				res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link));
 				if (res) {
 					res->base = base;
 					res->limit = limit;
@@ -650,8 +649,8 @@  static void ram_resource(device_t dev, u
 		return;
 	}
 	resource = new_resource(dev, index);
-	resource->base  = ((resource_t)basek) << 10;
-	resource->size  = ((resource_t)sizek) << 10;
+	resource->base = ((resource_t)basek) << 10;
+	resource->size = ((resource_t)sizek) << 10;
 	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
@@ -668,10 +667,10 @@  static void tolm_test(void *gp, struct d
 	*best_p = best;
 }
 
-static uint32_t find_pci_tolm(struct bus *bus)
+static u32 find_pci_tolm(struct bus *bus)
 {
 	struct resource *min;
-	uint32_t tolm;
+	u32 tolm;
 	min = 0;
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 	tolm = 0xffffffffUL;
@@ -697,8 +696,8 @@  static struct hw_mem_hole_info get_hw_me
 		mem_hole.node_id = -1;
 
 		for (i = 0; i < fx_devs; i++) {
-			uint32_t base;
-			uint32_t hole;
+			u32 base;
+			u32 hole;
 			base  = f1_read_config32(0x40 + (i << 3));
 			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 				continue;
@@ -714,9 +713,9 @@  static struct hw_mem_hole_info get_hw_me
 
 		//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 		if(mem_hole.node_id==-1) {
-			uint32_t limitk_pri = 0;
+			u32 limitk_pri = 0;
 			for(i=0; i<8; i++) {
-				uint32_t base, limit;
+				u32 base, limit;
 				unsigned base_k, limit_k;
 				base  = f1_read_config32(0x40 + (i << 3));
 				if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -735,18 +734,16 @@  static struct hw_mem_hole_info get_hw_me
 				limitk_pri = limit_k;
 			}
 		}
-
 		return mem_hole;
-
 }
 
 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 {
 	int i;
 	device_t dev;
-	uint32_t base, limit;
-	uint32_t hoist;
-	uint32_t hole_sizek;
+	u32 base, limit;
+	u32 hoist;
+	u32 hole_sizek;
 
 
 	//1. find which node has hole
@@ -776,22 +773,22 @@  static void disable_hoist_memory(unsigne
 		return;
 	}
 	hoist = pci_read_config32(dev, 0xf0);
-	if(hoist & 1)
+	if(hoist & 1) {
 		pci_write_config32(dev, 0xf0, 0);
-	else {
+	} else {
 		base = pci_read_config32(dev, 0x40 + (node_id << 3));
 		f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
 	}
 }
 
-static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
+static u32 hoist_memory(unsigned long hole_startk, int node_id)
 {
 	int i;
-	uint32_t carry_over;
+	u32 carry_over;
 	device_t dev;
-	uint32_t base, limit;
-	uint32_t basek;
-	uint32_t hoist;
+	u32 base, limit;
+	u32 basek;
+	u32 hoist;
 
 	carry_over = (4*1024*1024) - hole_startk;
 
@@ -848,11 +845,11 @@  static void amdk8_domain_set_resources(d
 	struct resource *res;
 #endif
 	unsigned long mmio_basek;
-	uint32_t pci_tolm;
+	u32 pci_tolm;
 	int i, idx;
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 	struct hw_mem_hole_info mem_hole;
-	unsigned reset_memhole = 1;
+	u32 reset_memhole = 1;
 #endif
 
 #if 0
@@ -909,7 +906,6 @@  static void amdk8_domain_set_resources(d
 		res->flags |= IORESOURCE_ASSIGNED;
 		res->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, res, "");
-
 	}
 #endif
 
@@ -953,10 +949,10 @@  static void amdk8_domain_set_resources(d
 
 		#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
-			uint32_t basek_pri;
+			u32 basek_pri;
 			for (i = 0; i < fx_devs; i++) {
-				uint32_t base;
-				uint32_t basek;
+				u32 base;
+				u32 basek;
 				base  = f1_read_config32(0x40 + (i << 3));
 				if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 					continue;
@@ -980,8 +976,8 @@  static void amdk8_domain_set_resources(d
 
 	idx = 0x10;
 	for(i = 0; i < fx_devs; i++) {
-		uint32_t base, limit;
-		unsigned basek, limitk, sizek;
+		u32 base, limit;
+		u32 basek, limitk, sizek;
 		base  = f1_read_config32(0x40 + (i << 3));
 		limit = f1_read_config32(0x44 + (i << 3));
 		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -1074,9 +1070,9 @@  static void amdk8_domain_set_resources(d
 
 }
 
-static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
+static u32 amdk8_domain_scan_bus(device_t dev, u32 max)
 {
-	unsigned reg;
+	u32 reg;
 	int i;
 	/* Unmap all of the HT chains */
 	for(reg = 0xe0; reg <= 0xec; reg += 4) {
@@ -1092,7 +1088,7 @@  static unsigned int amdk8_domain_scan_bu
 		device_t f0_dev;
 		f0_dev = __f0_dev[i];
 		if (f0_dev && f0_dev->enabled) {
-			uint32_t httc;
+			u32 httc;
 			httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
 			httc &= ~HTTC_RSP_PASS_PW;
 			if (!dev->link[0].disable_relaxed_ordering) {
@@ -1109,15 +1105,15 @@  static unsigned int amdk8_domain_scan_bu
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources   = amdk8_domain_read_resources,
-	.set_resources    = amdk8_domain_set_resources,
+	.read_resources	  = amdk8_domain_read_resources,
+	.set_resources	  = amdk8_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
-	.init             = 0,
-	.scan_bus         = amdk8_domain_scan_bus,
-	.ops_pci_bus      = &pci_cf8_conf1,
+	.init		  = 0,
+	.scan_bus	  = amdk8_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
-static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
+static u32 cpu_bus_scan(device_t dev, u32 max)
 {
 	struct bus *cpu_bus;
 	device_t dev_mc;
@@ -1142,9 +1138,9 @@  static unsigned int cpu_bus_scan(device_
 	get_option(&disable_siblings, "multi_core");
 #endif
 
-	// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
-	// How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
-
+	// for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0)
+	// How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
+	// and differ d0 and e0 single core
 	nb_cfg_54 = read_nb_cfg_54();
 
 	dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
@@ -1197,7 +1193,6 @@  static unsigned int cpu_bus_scan(device_
 					dev_f0->link[local_j].dev = dev_f0;
 				}
 			}
-
 		}
 
 		e0_later_single_core = 0;
@@ -1236,7 +1231,7 @@  static unsigned int cpu_bus_scan(device_
   			}
 		}
 
-		unsigned jj;
+		u32 jj;
 		if(e0_later_single_core || disable_siblings) {
 			jj = 0;
 		} else
@@ -1280,8 +1275,8 @@  static unsigned int cpu_bus_scan(device_
 						cpu->path.apic.apic_id += sysconf.apicid_offset;
 					} else
 					{
-					       if (cpu->path.apic.apic_id != 0)
-						       cpu->path.apic.apic_id += sysconf.apicid_offset;
+						if (cpu->path.apic.apic_id != 0)
+							cpu->path.apic.apic_id += sysconf.apicid_offset;
 					}
 				}
 				printk(BIOS_DEBUG, "CPU: %s %s\n",
@@ -1303,11 +1298,11 @@  static void cpu_bus_noop(device_t dev)
 }
 
 static struct device_operations cpu_bus_ops = {
-	.read_resources   = cpu_bus_noop,
-	.set_resources    = cpu_bus_noop,
+	.read_resources	  = cpu_bus_noop,
+	.set_resources	  = cpu_bus_noop,
 	.enable_resources = cpu_bus_noop,
-	.init             = cpu_bus_init,
-	.scan_bus         = cpu_bus_scan,
+	.init		  = cpu_bus_init,
+	.scan_bus	  = cpu_bus_scan,
 };
 
 static void root_complex_enable_dev(struct device *dev)