Patchwork add support for Asus P4S800-MX

login
register
about
Submitter David Borg
Date 2010-07-01 09:50:46
Message ID <AANLkTikzYojWNa5vlPlFVgARZdJKgTGPEKp6q5kP8N0p@mail.gmail.com>
Download mbox | patch
Permalink /patch/1570/
State Superseded
Headers show

Comments

David Borg - 2010-07-01 09:50:46
Patch to add support for the Asus P4S800-MX motherboard and SIS 963
chipset. Invalidates previous patch: [PATCH] add support for SIS963

If anyone has the output of superiotool -deV for the following working
boards, please forward them, so I can merge the functions
w836xx_unlock_memw_enable_2e and w836xx_memw_enable_2e, and maybe fix
the function w836xx_memw_enable which I believe has a typo, such that
                sio_mask(port, 0x24, 0x28, 0x28);
becomes : sio_mask(port, 0x24, 0x28, 0x38);

Motherboards:
Albatron - PM266A Pro
ASUS - A7V8X-MX SE
EPoX - EP-8K5A2
Shuttle - AK31
Tyan - S2498 (Tomcat K7M)
Termtek - TK-3370 (Rev:2.5B)
MSI - MS-6590 (KT4 Ultra)
MSI - MS-6712 (KT4V)
MSI - MS-7005 (651M-L)

Signed-off-by: David Borg <borg.db@gmail.com>

Regards,
David

Patch

Index: chipset_enable.c
===================================================================
--- chipset_enable.c	(revision 1064)
+++ chipset_enable.c	(working copy)
@@ -197,6 +197,25 @@ 
 	return ret;
 }
 
+static int enable_flash_sis963(struct pci_dev *dev, const char *name)
+{
+        uint8_t tmp;
+
+        /***************************************************************/
+        /* Initialise South-Bridge to enable communication with SuperIO
+         * for ROM access. No supporting documentation, however it works.
+         */
+
+        tmp = pci_read_byte(dev, 0x45);
+        tmp &= ~0x80;
+        tmp |= 0x40;
+        pci_write_byte(dev, 0x45, tmp);
+
+        /****************************************************************/
+
+        return 0;
+}
+
 /* Datasheet:
  *   - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
  *   - URL: http://www.intel.com/design/intarch/datashts/290562.htm
@@ -1448,6 +1467,7 @@ 
 	{0x1039, 0x0746, NT, "SiS", "746",		enable_flash_sis540},
 	{0x1039, 0x0748, NT, "SiS", "748",		enable_flash_sis540},
 	{0x1039, 0x0755, NT, "SiS", "755",		enable_flash_sis540},
+	{0x1039, 0x0963, OK, "SiS", "963",              enable_flash_sis963},
 	/* VIA northbridges */
 	{0x1106, 0x0585, NT, "VIA", "VT82C585VPX",	via_no_byte_merge},
 	{0x1106, 0x0595, NT, "VIA", "VT82C595",		via_no_byte_merge},
Index: board_enable.c
===================================================================
--- board_enable.c	(revision 1064)
+++ board_enable.c	(working copy)
@@ -44,6 +44,26 @@ 
 	OUTB(0xAA, port);
 }
 
+/* 
+ * Unlocks w836xx Super IO chips for write access
+ * Supported chips:
+ * W83627DHG, W83627EHF/EF/EHG/EG, W83627HF/F/HG/G, W83627THF/THG
+ * W83627DHG-P/PT, W83627UHG, W83637HF/HG, W83697HF/F/HG,
+ * W83697SF/UF/UG and W83L517D
+ * @return 1 if the chip was locked, otherwise 0
+ */
+uint8_t w836xx_unlock(uint16_t port)
+{
+	uint8_t lock = 0;
+	w836xx_ext_enter(port);
+	lock = sio_read(port, 0x26);
+	if (lock & 0x20) {
+		sio_write(port, 0x26, (lock & ~0x20));
+	}
+	w836xx_ext_leave(port);
+	return (lock & 0x20) >> 5;
+}
+
 /* Generic Super I/O helper functions */
 uint8_t sio_read(uint16_t port, uint8_t reg)
 {
@@ -351,7 +371,9 @@ 
 }
 
 /**
- * w83627: Enable MEMW# and set ROM size to max.
+ * Enable MEMW# and set ROM size to max.
+ * Supported chips:
+ * W83L517D, W83697HF/F/HG, W83697SF/UF/UG
  */
 static void w836xx_memw_enable(uint16_t port)
 {
@@ -389,6 +411,13 @@ 
 	return 0;
 }
 
+static int w836xx_unlock_memw_enable_2e(void)
+{
+	w836xx_unlock(0x2E);
+	w836xx_memw_enable(0x2E);
+	return 0;
+}
+
 /**
  *
  */
@@ -1595,6 +1624,7 @@ 
 	{0x8086, 0x1A30, 0x1043, 0x8088,  0x8086, 0x24C3, 0x1043, 0x8089, NULL,          NULL,         NULL,          "ASUS",        "P4B533-E",              0,   NT, intel_ich_gpio22_raise},
 	{0x8086, 0x24D3, 0x1043, 0x80A6,  0x8086, 0x2578, 0x1043, 0x80F6, NULL,          NULL,         NULL,          "ASUS",        "P4C800-E Deluxe",       0,   OK, intel_ich_gpio21_raise},
 	{0x8086, 0x2570, 0x1043, 0x80F2,  0x105A, 0x3373, 0x1043, 0x80F5, NULL,          NULL,         NULL,          "ASUS",        "P4P800-E Deluxe",       0,   OK, intel_ich_gpio21_raise},
+	{0x1039, 0x0963,      0,      0,  0x1039, 0x0661,      0,      0, "^P4S800-MX$", NULL,	       NULL,	      "ASUS",	     "P4S800-MX",	    512,   OK, w836xx_unlock_memw_enable_2e},
 	{0x10B9, 0x1541,      0,      0,  0x10B9, 0x1533,      0,      0, "^P5A$",       "asus",       "p5a",         "ASUS",        "P5A",                   0,   OK, board_asus_p5a},
 	{0x10DE, 0x0030, 0x1043, 0x818a,  0x8086, 0x100E, 0x1043, 0x80EE, NULL,          NULL,         NULL,          "ASUS",        "P5ND2-SLI Deluxe",      0,   OK, nvidia_mcp_gpio10_raise},
 	{0x1106, 0x3149, 0x1565, 0x3206,  0x1106, 0x3344, 0x1565, 0x1202, NULL,          NULL,         NULL,          "Biostar",     "P4M80-M4",              0,   OK, it8705f_write_enable_2e},