Patchwork Add ICH9 Engineering sample to chipset enables

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Submitter Carl-Daniel Hailfinger
Date 2009-08-21 14:33:17
Message ID <4A8EB02D.9000607@gmx.net>
Download mbox | patch
Permalink /patch/158/
State Accepted
Commit r696
Headers show

Comments

Carl-Daniel Hailfinger - 2009-08-21 14:33:17
Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr> reported that flashrom
didn't recognize her ICH9 LPC controller. According to
http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was only
used for an engineering sample. No intel doc mentions this ID at all.

Anne, could you reply to this mail with "lspci -nnvvvxxx" as attachment?
Thanks! This list accepts attachments.

If the patch below is what you had in mind and detecting the chipset
works for you, please reply with
Acked-by: Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr>

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

This patch will also appear at the top of
http://patchwork.coreboot.org/project/flashrom/list/ so if you have
trouble extracting the patch from this mail, you can download it from there.
Carl-Daniel Hailfinger - 2009-08-21 17:27:31
bouncing this mail...

On 21.08.2009 18:55, LE COQ ANNYVONNE wrote:
> Hello,
> I have to leave my office now. I'll send the lspci result on Monday.
> I'm working on an INTEL demo board called GreenCity:
> 2 Nehalem processors, ICH9 + Tylersburg. 
> The problem is that I'm not able to flash a new BIOS ...
>
> I'm OK with the patch below, I've tested it on the GreenCity MotherBoard
> Have a good week end
> Anne
>
Carl-Daniel Hailfinger - 2009-08-21 17:28:57
bouncing this mail...

On 21.08.2009 18:41, LE COQ ANNYVONNE wrote:
> Acked-by: Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr>
>
> Hi Carl-Daniel,
>
> It's the modification I've done to accept the ICH9, and it works fine. I just mention "ICH9" instead of "ICH9 Engineering Sample", but I don't think it's very important.
>
> My problem now is that the opcode 06 is unknown in the opcode table.
> To continue my test, I replace one of unused opcode (0B9H) by 06 and it's better. But it's not a good solution...
> Then, after that, I can only read, write and erase my flash till A000H.
> I think it's because I use the ICH9 in descriptor mode.
> I have the following fault: 
> ERROR at 0x0000a000: Expected=0xff, Read=0x00
> Have you got an idea about this issue ?
> Thanks
> Anne
>
Carl-Daniel Hailfinger - 2009-08-21 17:31:33
On 21.08.2009 16:33, Carl-Daniel Hailfinger wrote:
> Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr> reported that flashrom
> didn't recognize her ICH9 LPC controller. According to
> http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was only
> used for an engineering sample. No intel doc mentions this ID at all.
>
> Acked-by: Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr>
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
>   

Committed in r696.

Regards,
Carl-Daniel

Patch

Index: flashrom-ich9_engineeringsample/chipset_enable.c
===================================================================
--- flashrom-ich9_engineeringsample/chipset_enable.c	(Revision 695)
+++ flashrom-ich9_engineeringsample/chipset_enable.c	(Arbeitskopie)
@@ -1012,6 +1012,7 @@ 
 	{0x8086, 0x2919, OK, "Intel", "ICH9M",		enable_flash_ich9},
 	{0x8086, 0x2917, OK, "Intel", "ICH9M-E",	enable_flash_ich9},
 	{0x8086, 0x2916, OK, "Intel", "ICH9R",		enable_flash_ich9},
+	{0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
 	{0x8086, 0x1234, NT, "Intel", "MPIIX",		enable_flash_piix4},
 	{0x8086, 0x7000, OK, "Intel", "PIIX3",		enable_flash_piix4},
 	{0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M",	enable_flash_piix4},