===================================================================
@@ -80,12 +80,13 @@
//set GPIO to input mode
#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, 0x60,((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, 0x60,((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, 0x60,((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, 0x60,((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, 0x60,((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, 0x60,((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, 0x60,((0<<4)|(0<<2)|(0<<0)),/* GPIO (match factory) */
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
===================================================================
@@ -15,22 +15,15 @@
const unsigned int *register_values, int max)
{
int i;
- unsigned val;
- val = inl(control);
- val &= 0xfffffffe;
- outl(val, control);
-
- outl(0, index);
+ outb(0, control);
+ outb(0, index);
for (i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);
}
- val = inl(control);
- val |= 1;
- outl(val, control);
}
#define ANACTRL_IO_BASE 0x8800
@@ -122,49 +115,105 @@
static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
unsigned *io_base)
{
- static const unsigned int ctrl_conf_master[] = {
+ static const unsigned int ctrl_conf_MB[] = {
+#ifdef CK804_MB_SETUP
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0x00ffffff, 0x20000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x64), 0xffff00ff, 0x00008400,
+ CK804_MB_SETUP
+#endif
+ };
+
+ static const unsigned int ctrl_conf_master_A[] = {
+
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x1c), 0xffffffff, 0x000000ff,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x04), 0xffffffff, 0x00000001,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x5c), 0x00000000, 0x00800003,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x60), 0x00000000, 0x00800000,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffffff, 0x00000000,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x68), 0x00000000, 0x00008400,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x64), 0x00000000, 0x00008200,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x60), 0x00000000, 0x00008000,
+
+ RES_PORT_IO_8, 0x82c3, 0x9e, 0x04,
+ RES_PORT_IO_8, 0x84cd, 0xff, 0x01,
+ RES_PORT_IO_8, 0x8424, 0xff, 0x00,
+ RES_PORT_IO_8, 0x8480, 0xb7, 0x01,
+ RES_PORT_IO_8, 0x82c3, 0x07, 0x01,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x68), 0x00000000, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x64), 0x00000000, 0x00000000,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x50), 0x00000000, 0x00005000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x04), 0xffffffff, 0x00000001,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xa8), 0xffffff00, 0x05ff0400,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x1c), 0xffffff00, 0x00000010,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x88), 0xffffff00, 0x00000030,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x60), 0x00000000, 0x00008000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x64), 0x00000000, 0x00008400,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x68), 0x00000000, 0x00008800,
+
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xffffffff, 0x00000000,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x88), 0xffffff00, 0x000000b0,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x60), 0xffffffff, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x64), 0xffffffff, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x68), 0xffffffff, 0x00000000,
+
+ };
+
+ static const unsigned int ctrl_conf_master_B[] = {
+ RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x84), 0xffff0000, 0x000000ef,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xac), 0xffffff00, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f,
+#if CK804_USE_NIC == 1
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 0, 0xe4), 0xffffffff, 0x00800000,
+#endif
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 0, 0xe8), 0xffffffff, 0x60000000,
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 0, 0x44), 0x00000000, 0xfefffc00,
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 1, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x2, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x2, 1, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x4, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x4, 1, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x6, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x7, 0, 0x40), 0x00000000, 0xcb8410de,
+ RES_PCI_IO, PCI_ADDR(0, 0x8, 0, 0x40), 0x00000000, 0xcb8410de,
+
+ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffefd, 0x00000002,
+ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x00000061,
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffffffff, 0x00800000,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000,
-
-#ifdef CK804_MB_SETUP
- CK804_MB_SETUP
-#endif
-
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100,
-
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
-
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
-
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xff7fffff, 0x04000000,
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xffffffff, 0x00320000,
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0x00000003, 0x013f3c03, /* Double check */
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xffffffff, 0x00080000, /* Double check */
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7c), 0xffffff7f, 0x00000010, /* Double check */
+ RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xf8), 0xffffffff, 0x00000010,
+
+ RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x08), 0xffffffff, 0x00000050,
+ RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x50), 0xffffffff, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xf8), 0xffffffff, 0x00000010,
/* Activate master port on primary SATA controller. */
+ RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x08), 0xffffffff, 0x00000050,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000,
@@ -176,6 +225,7 @@
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x08), 0xffffffff, 0x00000050,
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000,
@@ -187,19 +237,68 @@
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x3c), 0xffffffff, 0x02000000,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00070000,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x48), 0xfff8ffff, 0x00000007,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x01440000,
+ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000,
+
+#if CK804_USE_NIC == 1
+ RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0x4c), 0xffffffff, 0x10000000, /**/
+ RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0x60), 0xffffffff, 0x0000000f, /**/
+ RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, /**/
+#endif
+
+ RES_PCI_IO, PCI_ADDR(0, 0x1, 0, 0xe8), 0xbfffffff, 0x00000000,
+
+ RES_PORT_IO_32, 0x8010, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, 0x801c, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, 0x8084, 0xfffff0ff, 0x00000000,
+ RES_PORT_IO_32, 0x8088, 0xfffff0ff, 0x00000800,
+ RES_PORT_IO_32, 0x8090, 0xfffff0ff, 0x00000000,
+ RES_PORT_IO_32, 0x80a4, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, 0x80b4, 0xffffffff, 0x00000000,
+
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x5c, 0xfdffffff, 0x00000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x64, 0xffffffff, 0x00008000,
+
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04d7, 0x51407120,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00010010,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x98, 0xffffffff, 0x00000000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
+
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0x0fff0000, 0x8000f000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xff00ff00, 0x00100010,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, 0xff00ffff, 0x00500000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0xff00ffff, 0x00e00000,
+
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xa0), 0xffffffff, 0x00000000, /**/
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000200,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000,
+
+ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x6c), 0xffffffff, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0,
+
+ RES_PORT_IO_32, 0x80ac, 0xffffffff, 0x00000000,
+
+#if 0
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
+
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
+#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
-
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
//SYSCTRL
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
#if CK804_USE_NIC == 1
- RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
@@ -211,13 +310,17 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
#endif
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffefffff, 0x00000000,
+ RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x88), 0x00000000, 0x00000006,
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffffffff, 0x00100000,
+
};
static const unsigned int ctrl_conf_multiple[] = {
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
};
- static const unsigned int ctrl_conf_slave[] = {
+ static const unsigned int ctrl_conf_slave_A[] = {
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
@@ -240,13 +343,14 @@
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff,
+ //RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04d7, 0x51407120,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
+ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x98, 0xffffffff, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
@@ -266,9 +370,6 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
-/* This line doesn't exist in the non-CAR version. */
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
-
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
#if CK804_USE_NIC == 1
@@ -280,26 +381,26 @@
#endif
};
+ static const unsigned int ctrl_conf_slave_B[] = {
+ };
+
int j;
+
+ setup_resource_map_x_offset(ctrl_conf_MB,
+ ARRAY_SIZE(ctrl_conf_MB),
+ PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]);
+
for (j = 0; j < ck804_num; j++) {
if (busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_master,
- ARRAY_SIZE(ctrl_conf_master),
+ setup_resource_map_x_offset(ctrl_conf_master_A,
+ ARRAY_SIZE(ctrl_conf_master_A),
PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]);
- if (ck804_num > 1)
- setup_resource_map_x_offset(ctrl_conf_multiple,
- ARRAY_SIZE(ctrl_conf_multiple),
- PCI_DEV(0, CK804_DEVN_BASE, 0), 0);
-
- continue;
- }
-
- setup_resource_map_x_offset(ctrl_conf_slave,
- ARRAY_SIZE(ctrl_conf_slave),
+ } else {
+ setup_resource_map_x_offset(ctrl_conf_slave_A,
+ ARRAY_SIZE(ctrl_conf_slave_A),
PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
- }
+ }
- for (j = 0; j < ck804_num; j++) {
/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
/* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
/* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */
@@ -315,6 +416,22 @@
io_base[j] + ANACTRL_IO_BASE + 0xc4,
io_base[j] + ANACTRL_IO_BASE + 0xc8,
cpu_ss_tbl, 64);
+
+ if (busn[j] == 0) {
+ setup_resource_map_x_offset(ctrl_conf_master_B,
+ ARRAY_SIZE(ctrl_conf_master_B),
+ PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]);
+ if (ck804_num > 1)
+ setup_resource_map_x_offset(ctrl_conf_multiple,
+ ARRAY_SIZE(ctrl_conf_multiple),
+ PCI_DEV(0, CK804_DEVN_BASE, 0), 0);
+
+ continue;
+ } else {
+ setup_resource_map_x_offset(ctrl_conf_slave_B,
+ ARRAY_SIZE(ctrl_conf_slave_B),
+ PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
+ }
}
}
@@ -338,6 +455,13 @@
}
}
+#if 0
+/* Add an extra one to compare with values from factory */
+ busn[ck804_num] = 0x80;
+ io_base[ck804_num] = 0x1000;
+ ck804_num++;
+#endif
+
ck804_early_set_port(ck804_num, busn, io_base);
ck804_early_setup(ck804_num, busn, io_base);
ck804_early_clear_port(ck804_num, busn, io_base);
@@ -358,6 +482,18 @@
{
set_bios_reset();
+
+ outl(0, 0x849c);
+ outl(0, 0x8498);
+ outl(0, 0x8494);
+ outl(0, 0x8490);
+ outl(0, 0x848c);
+ outl(0, 0x8488);
+ outl(0, 0x8484);
+ outl(0, 0x8480);
+ inb(0x8480);
+ outb(0xaa, 0x8480);
+
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
These two patches make the SerialICE output match a lot better. I'm not sure which part is the magic one, but my board works better on a reset now. I may get around to cleaning it up so that only things that matter get changed, but it isn't likely to happen very soon. I'm not suggesting that this should be applied, but I'd like to save anyone else who needs to do this some work. If I were to apply it, I'd force most of the extra stuff into the CK804_MB_SETUP, or something similar, since I've only tested this on s2895. Signed-off-by: Myles Watson <mylesgw@gmail.com> Thanks, Myles