Patchwork AMIC A25LxxPx

login
register
about
Submitter Daniel Lenski
Date 2010-07-12 20:46:52
Message ID <1278967612.4750.287.camel@basashi>
Download mbox | patch
Permalink /patch/1618/
State Accepted
Commit r1096
Headers show

Comments

Daniel Lenski - 2010-07-12 20:46:52
This patch adds the following chips, all untested, based on the AMIC
datasheets:
	http://www.amictechnology.com/pdf/A25L20P.pdf covers:
		AMIC A25L05PT
		AMIC A25L05PU
		AMIC A25L10PT
		AMIC A25L10PU
		AMIC A25L20PT
		AMIC A25L20PU
	http://www.amictechnology.com/pdf/A25L16P.pdf covers:
		AMIC A25L16PT
		AMIC A25L16PU

In comments, it also clarifies the situation surrounding the A25L40PT
and A25L40PU chips, which share the same RDID values, despite the fact
that their erase block layouts are different.  Rudolf Marek tested and
confirmed the distinct erase block layouts of these chips, so I also
marked them as TEST_OK_PREW.

Finally, it adds a pretty-printer for the AMIC SPI chips, and a generic
AMIC chip type.

Signed-off-by: Daniel Lenski <dlenski@gmail.com>
Daniel Lenski - 2010-07-18 22:50:21
On Mon, 2010-07-12 at 16:46 -0400, Daniel Lenski wrote:
> This patch adds the following chips, all untested, based on the AMIC
> datasheets:
> 	http://www.amictechnology.com/pdf/A25L20P.pdf covers:
> 		AMIC A25L05PT
> 		AMIC A25L05PU
> 		AMIC A25L10PT
> 		AMIC A25L10PU
> 		AMIC A25L20PT
> 		AMIC A25L20PU
> 	http://www.amictechnology.com/pdf/A25L16P.pdf covers:
> 		AMIC A25L16PT
> 		AMIC A25L16PU
> 
> In comments, it also clarifies the situation surrounding the A25L40PT
> and A25L40PU chips, which share the same RDID values, despite the fact
> that their erase block layouts are different.  Rudolf Marek tested and
> confirmed the distinct erase block layouts of these chips, so I also
> marked them as TEST_OK_PREW.
> 
> Finally, it adds a pretty-printer for the AMIC SPI chips, and a generic
> AMIC chip type.
> 
> Signed-off-by: Daniel Lenski <dlenski@gmail.com>

Did this patch get forgotten?

It added the AMIC SPI chips requested by Carl-Daniel Hailfinger.  Pretty
straightforward stuff.  Please let me know if there are any changes
needed.

Dan
Carl-Daniel Hailfinger - 2010-07-22 11:58:39
Hi Daniel,

thanks a lot for your patch.

On 12.07.2010 22:46, Daniel Lenski wrote:
> This patch adds the following chips, all untested, based on the AMIC
> datasheets:
> 	http://www.amictechnology.com/pdf/A25L20P.pdf covers:
> 		AMIC A25L05PT
> 		AMIC A25L05PU
> 		AMIC A25L10PT
> 		AMIC A25L10PU
> 		AMIC A25L20PT
> 		AMIC A25L20PU
> 	http://www.amictechnology.com/pdf/A25L16P.pdf covers:
> 		AMIC A25L16PT
> 		AMIC A25L16PU
>
> In comments, it also clarifies the situation surrounding the A25L40PT
> and A25L40PU chips, which share the same RDID values, despite the fact
> that their erase block layouts are different.  Rudolf Marek tested and
> confirmed the distinct erase block layouts of these chips, so I also
> marked them as TEST_OK_PREW.
>
> Finally, it adds a pretty-printer for the AMIC SPI chips, and a generic
> AMIC chip type.
>
> Signed-off-by: Daniel Lenski <dlenski@gmail.com>
>   

I have changed the whitespace in a few places, added the .unlock
function to the chip definitions and added the 0x60 chip erase command
to the A25L16P* family chips.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
and committed in r1096.

Side note: If anyone is looking for the datasheet for the
not-yet-supported A25L032 family, here it is:
http://www.amictechnology.com/pdf/A25L032.pdf

Regards,
Carl-Daniel
Daniel Lenski - 2010-07-22 13:35:45
On Thu, Jul 22, 2010 at 7:58 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006@gmx.net> wrote:
> Side note: If anyone is looking for the datasheet for the
> not-yet-supported A25L032 family, here it is:
> http://www.amictechnology.com/pdf/A25L032.pdf

I took a look at this.  Similar to the others from AMIC but...

Incredibly, the data sheet states two different device ID values on
page 31 (it's either 0x3016 or 0x4016).  Does anyone know which is
right?

This device has *two* status registers, with separate RDSR-1 and
RDSR-2 commands, but a combined WRSR command.  The first has the
standard block protect bits BP0-2, while the second has an "All
protect" (APT) bit which overrides the BP bits.  I think the unlock
procedure would have to be modified to account for this APT bit.

Dan
Carl-Daniel Hailfinger - 2010-07-23 12:49:58
On 22.07.2010 15:35, Daniel Lenski wrote:
> On Thu, Jul 22, 2010 at 7:58 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006@gmx.net> wrote:
>   
>> Side note: If anyone is looking for the datasheet for the
>> not-yet-supported A25L032 family, here it is:
>> http://www.amictechnology.com/pdf/A25L032.pdf
>>     
>
> I took a look at this.  Similar to the others from AMIC but...
>
> Incredibly, the data sheet states two different device ID values on
> page 31 (it's either 0x3016 or 0x4016).  Does anyone know which is
> right?
>   

According to my datsheets, the following is true:
0x7f37 0x2025 is A25L16PT (top)
0x7f37 0x2015 is A25L16PU (bottom)
The chips above are already supported.

The chips below are all unsupported:
http://www.amictechnology.com/pdf/A25L512.pdf
http://www.amictechnology.com/pdf/A25L010.pdf
http://www.amictechnology.com/pdf/A25L020.pdf
http://www.amictechnology.com/pdf/A25L040.pdf
http://www.amictechnology.com/pdf/A25L080.pdf
http://www.amictechnology.com/pdf/A25L016.pdf
http://www.amictechnology.com/pdf/A25L032.pdf
http://www.amictechnology.com/pdf/A25LQ032.pdf
IDs:
0x37 0x3010 is A25L512 (uniform 4k sectors)
0x37 0x3011 is A25L010 (uniform 4k sectors)
0x37 0x3012 is A25L020 (uniform 4k sectors)
0x37 0x3013 is A25L040 (uniform 4k sectors)
0x37 0x3014 is A25L080 (uniform 4k sectors)
0x37 0x3015 is A25L016 (uniform 4k sectors)
0x37 0x3016 is A25L032 (uniform 4k sectors)
0x37 0x4016 is A25LQ032 (uniform 4k sectors)
Please note that the IDs of the newer chips all use AMIC_ID_NOPREFIX
instead of AMIC_ID, and that means they use probe_spi_rdid instead of
probe_spi_rdid4.


> This device has *two* status registers, with separate RDSR-1 and
> RDSR-2 commands, but a combined WRSR command.  The first has the
> standard block protect bits BP0-2, while the second has an "All
> protect" (APT) bit which overrides the BP bits.  I think the unlock
> procedure would have to be modified to account for this APT bit.
>   

You can either set .unlock=NULL or write a new unlock function. If you
decide to write a new unlock function, please note that you'll need an
audit of all SPI programmer drivers to check whether they can deal with
such writes. I can help with such an audit, but I'd be happy if I could
postpone that work a bit because my TODO list is huge. OTOH, drivers
without unlock should be mergeable quickly.

Side note: Right now we have the AMIC chips after the Atmel chips in
flashchips.c instead of placing them directly after the AMD chips. Not
sure if a move makes sense (good for consistency, but it will mess up
svn blame).

Regards,
Carl-Daniel

Patch

Index: spi25.c
===================================================================
--- spi25.c	(revision 1075)
+++ spi25.c	(working copy)
@@ -328,6 +328,16 @@ 
 }
 
 /* Prettyprint the status register. Works for
+ * AMIC A25L series
+ */
+void spi_prettyprint_status_register_amic_a25l(uint8_t status)
+{
+	msg_cdbg("Chip status register: Status Register Write Disable "
+		     "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+	spi_prettyprint_status_register_common(status);
+}
+
+/* Prettyprint the status register. Works for
  * ST M25P series
  * MX MX25L series
  */
@@ -389,6 +399,10 @@ 
 	status = spi_read_status_register();
 	msg_cdbg("Chip status register is %02x\n", status);
 	switch (flash->manufacture_id) {
+	case AMIC_ID:
+		if ((flash->model_id & 0xff00) == 0x2000)
+		    spi_prettyprint_status_register_amic_a25l(status);
+		break;
 	case ST_ID:
 		if (((flash->model_id & 0xff00) == 0x2000) ||
 		    ((flash->model_id & 0xff00) == 0x2500))
Index: flashchips.c
===================================================================
--- flashchips.c	(revision 1075)
+++ flashchips.c	(working copy)
@@ -1155,17 +1155,206 @@ 
 		.read		= read_memmapped,
 	},
 
-	/* The next two chip definitions have top/bottom boot blocks, but has no
-	device differentiation between the two */
+	/* AMIC */
+
 	{
 		.vendor		= "AMIC",
+		.name		= "A25L05PT",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L05PT,
+		.total_size	= 64,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{32 * 1024, 1},
+					{16 * 1024, 1},
+					{8 * 1024, 1},
+					{4 * 1024, 2},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {64 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L05PU",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L05PU,
+		.total_size	= 64,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{4 * 1024, 2},
+					{8 * 1024, 1},
+					{16 * 1024, 1},
+					{32 * 1024, 1},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {64 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L10PT",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L10PT,
+		.total_size	= 128,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{64 * 1024, 1},
+					{32 * 1024, 1},
+					{16 * 1024, 1},
+					{8 * 1024, 1},
+					{4 * 1024, 2},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {128 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L10PU",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L10PU,
+		.total_size	= 128,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{4 * 1024, 2},
+					{8 * 1024, 1},
+					{16 * 1024, 1},
+					{32 * 1024, 1},
+					{64 * 1024, 1},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {128 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L20PT",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L20PT,
+		.total_size	= 256,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{64 * 1024, 3},
+					{32 * 1024, 1},
+					{16 * 1024, 1},
+					{8 * 1024, 1},
+					{4 * 1024, 2},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {256 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L20PU",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L20PU,
+		.total_size	= 256,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{4 * 1024, 2},
+					{8 * 1024, 1},
+					{16 * 1024, 1},
+					{32 * 1024, 1},
+					{64 * 1024, 3},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {256 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	/* The A25L40P{T,U} chips are distinguished by their
+	 * erase block layouts, but without any distinction in RDID.
+	 * This inexplicable quirk was verified by Rudolf Marek
+	 * and discussed on the Flashrom mailing list on 2010-07-12.
+	 */
+	{
+		.vendor		= "AMIC",
 		.name		= "A25L40PT",
 		.bustype	= CHIP_BUSTYPE_SPI,
 		.manufacture_id	= AMIC_ID,
-		.model_id	= AMIC_A25L40P,
+		.model_id	= AMIC_A25L40PT,
 		.total_size	= 512,
 		.page_size	= 256,
-		.tested		= TEST_OK_PRW,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid4,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -1193,10 +1382,10 @@ 
 		.name		= "A25L40PU",
 		.bustype	= CHIP_BUSTYPE_SPI,
 		.manufacture_id	= AMIC_ID,
-		.model_id	= AMIC_A25L40P,
+		.model_id	= AMIC_A25L40PU,
 		.total_size	= 512,
 		.page_size	= 256,
-		.tested		= TEST_OK_PRW,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid4,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -1252,6 +1441,68 @@ 
 
 	{
 		.vendor		= "AMIC",
+		.name		= "A25L16PT",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L16PT,
+		.total_size	= 2048,
+		.page_size	= 256,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{64 * 1024, 31},
+					{32 * 1024, 1},
+					{16 * 1024, 1},
+					{8 * 1024, 1},
+					{4 * 1024, 2},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {2048 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
+		.name		= "A25L16PU",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= AMIC_A25L16PU,
+		.total_size	= 2048,
+		.page_size	= 256,
+		.tested		= TEST_OK_PRW,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = {
+					{4 * 1024, 2},
+					{8 * 1024, 1},
+					{16 * 1024, 1},
+					{32 * 1024, 1},
+					{64 * 1024, 31},
+				},
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { { 2048 * 1024, 1 } },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "AMIC",
 		.name		= "A29002B",
 		.bustype	= CHIP_BUSTYPE_PARALLEL,
 		.manufacture_id	= AMIC_ID_NOPREFIX,
@@ -6491,7 +6742,23 @@ 
 		.read		= read_memmapped,
 	},
 
+	/* generic SPI chips */
 	{
+		.vendor		= "AMIC",
+		.name		= "unknown AMIC SPI chip",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= AMIC_ID,
+		.model_id	= GENERIC_DEVICE_ID,
+		.total_size	= 0,
+		.page_size	= 256,
+		.tested		= TEST_BAD_PREW,
+		.probe		= probe_spi_rdid4,
+		.probe_timing	= TIMING_ZERO,
+		.write		= NULL,
+		.read		= NULL,
+	},
+
+	{
 		.vendor		= "Atmel",
 		.name		= "unknown Atmel SPI chip",
 		.bustype	= CHIP_BUSTYPE_SPI,
Index: flashchips.h
===================================================================
--- flashchips.h	(revision 1075)
+++ flashchips.h	(working copy)
@@ -75,8 +75,19 @@ 
 
 #define AMIC_ID			0x7F37	/* AMIC */
 #define AMIC_ID_NOPREFIX	0x37	/* AMIC */
-#define AMIC_A25L40P		0x2013
-#define AMIC_A25L80P		0x2014
+#define AMIC_A25L05PT		0x2020
+#define AMIC_A25L05PU		0x2010
+#define AMIC_A25L10PT		0x2021
+#define AMIC_A25L10PU		0x2011
+#define AMIC_A25L20PT		0x2022
+#define AMIC_A25L20PU		0x2012
+#define AMIC_A25L40PT		0x2013	/* Datasheet says T and U have
+					   same device ID, and confimed by
+					   hardware testing. */
+#define AMIC_A25L40PU		0x2013
+#define AMIC_A25L80P		0x2014	/* Seems that no A25L80PT exists */
+#define AMIC_A25L16PT		0x2025
+#define AMIC_A25L16PU		0x2015
 #define AMIC_A29002B		0x0d
 #define AMIC_A29002T		0x8C	/* Same as A290021T */
 #define AMIC_A29040B		0x86