Patchwork Enable Direct TMDS for the RS690

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Submitter Daniel Toussaint
Date 2009-08-21 18:36:34
Message ID <6cb69d4a0908211136i45e5fbf7x323d2ff78cb09129@mail.gmail.com>
Download mbox | patch
Permalink /patch/167/
State Accepted
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Comments

Daniel Toussaint - 2009-08-21 18:36:34
Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
monitors.
Signed-off-by: Libra Li <libra.li@technexion.com>
ron minnich - 2009-08-24 14:54:09
This is a nice job. I am inclined to ack it but I don't know much
about this chipset and have no way to test any potential issues for
the 690 -- any comment from AMD?

ron
Marc Jones - 2009-08-25 18:07:57
On Fri, Aug 21, 2009 at 12:36 PM, Daniel Toussaint<daniel@dmhome.net> wrote:
>
> Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
> monitors.
> Signed-off-by: Libra Li <libra.li@technexion.com>
>

Hi,
Thanks for the patch.

Why add the code to step 6 in rs690_gfx.c when there seems to be a
spot reserved for it in  step 2?

	/* step 2, TMDS, (only need if CMOS option is enabled) */
	if (cfg->gfx_tmds) {
	}


Marc
Libra Li - 2009-08-26 01:49:49
Hello,

        I had reference "AMD RS690 ASIC Family Register Programming
Requirements". It's in "Chapter 6 PCIE Initialization for TMDS". That is
show "step 6".
        Thanks.



2009/8/26 Marc Jones <marcj303@gmail.com>

> On Fri, Aug 21, 2009 at 12:36 PM, Daniel Toussaint<daniel@dmhome.net>
> wrote:
> >
> > Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
> > monitors.
> > Signed-off-by: Libra Li <libra.li@technexion.com>
> >
>
> Hi,
> Thanks for the patch.
>
> Why add the code to step 6 in rs690_gfx.c when there seems to be a
> spot reserved for it in  step 2?
>
>        /* step 2, TMDS, (only need if CMOS option is enabled) */
>        if (cfg->gfx_tmds) {
>        }
>
>
> Marc
>
>
> --
> http://marcjonesconsulting.com
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
Marc Jones - 2009-08-26 16:05:02
On Tue, Aug 25, 2009 at 7:49 PM, Libra Li<librali1977@gmail.com> wrote:
> Hello,
>
>         I had reference "AMD RS690 ASIC Family Register Programming
> Requirements". It's in "Chapter 6 PCIE Initialization for TMDS". That is
> show "step 6".
>         Thanks.
>

I see. Looks good to me. Thanks for the contribution.

I am not setup to test this but it is needed by those using TDMS.

Acked-by: Marc Jones <marcj303@gmail.com>

and checked in: r4585

Marc

Patch

Index: src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- src/southbridge/amd/rs690/rs690_pcie.c	(revision 4559)
+++ src/southbridge/amd/rs690/rs690_pcie.c	(working copy)
@@ -87,18 +87,21 @@ 
 		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
 			   PCIE_GFX_COMPLIANCE))) {
 	}
-	/* step 3 Power Down Control for Southbridge */
-	reg = nbpcie_p_read_index(dev, 0xa2);
 
-	switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
-	case 1:
-		nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
-		break;
-	case 2:
-		nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
-		break;
-	default:
-		break;
+        if (!cfg->gfx_tmds){
+		/* step 3 Power Down Control for Southbridge */
+		reg = nbpcie_p_read_index(dev, 0xa2);
+
+		switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
+		case 1:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+			break;
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+			break;
+		default:
+			break;
+		}
 	}
 }
 
Index: src/southbridge/amd/rs690/rs690_gfx.c
===================================================================
--- src/southbridge/amd/rs690/rs690_gfx.c	(revision 4559)
+++ src/southbridge/amd/rs690/rs690_gfx.c	(working copy)
@@ -471,7 +471,49 @@ 
 	/* done by enable_pci_bar3() before */
 
 	/* step 6 SBIOS compile flags */
+        if (cfg->gfx_tmds) {
+                /* step 6.2.2 Clock-Muxing Control */
+                /* step 6.2.2.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
 
+                /* step 6.2.2.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+
+                /* step 6.2.2.3 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+
+                /* step 6.2.3 Lane-Muxing Control */
+                /* step 6.2.3.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+
+                /* step 6.2.4 Received Data Control */
+                /* step 6.2.4.1 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+
+                /* step 6.2.4.2 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+
+                /* step 6.2.4.3 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+
+                /* step 6.2.4.4 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+
+                /* step 6.2.5 PLL Power Down Control */
+                /* step 6.2.5.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+
+                /* step 6.2.6 Driving Strength Control */
+                /* step 6.2.6.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+
+                /* step 6.2.6.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+        }
+
+        printk_info("rs690_gfx_init step6.\n");
+
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
 	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
 	if (cfg->gfx_compliance) {