Patchwork kconfig support for MSI MS-6178

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Submitter Uwe Hermann
Date 2009-08-22 23:08:28
Message ID <20090822230828.GC11813@greenwood>
Download mbox | patch
Permalink /patch/170/
State Accepted
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Comments

Uwe Hermann - 2009-08-22 23:08:28
See patch.

Thanks to everyone on IRC for the help!

Builds fine, but booting has CPU issues. Boot log attached.


Uwe.

Patch

Finish kconfig support for the MSI MS-6178.

 - i82801xx_smbus.o is disabled for now, it's not used anyway I think.

 - HAVE_OPTION_TABLE is set to 'n' as this board currently doesn't have
   a cmos.layout file.

 - devicetree.cb is updated from the current Config.lb contents.

 - option_table.o building is optional in src/arch/i386/Makefile.inc,
   using CONFIG_HAVE_OPTION_TABLE.

The code builds fine, and seems to also boot ok for some time, but
then there's a CPU related error:

  Initializing CPU #0
  CPU: vendor Intel device 665
  CPU: family 06, model 06, stepping 05
  Unknown cpu

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/southbridge/intel/i82801xx/Makefile.inc
===================================================================
--- src/southbridge/intel/i82801xx/Makefile.inc	(Revision 4561)
+++ src/southbridge/intel/i82801xx/Makefile.inc	(Arbeitskopie)
@@ -25,7 +25,7 @@ 
 driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_nic.o
 driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_pci.o
 driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_sata.o
-driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_smbus.o
+# driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_smbus.o
 driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_usb.o
 driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_usb_ehci.o
 
@@ -34,3 +34,5 @@ 
 
 # TODO: What about cmos_failover.c?
 
+# TODO: Fix and enable i82801xx_smbus.o later.
+
Index: src/mainboard/msi/Kconfig
===================================================================
--- src/mainboard/msi/Kconfig	(Revision 4561)
+++ src/mainboard/msi/Kconfig	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 	select SOUTHBRIDGE_INTEL_I82801XX
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
+	select CONSOLE_SERIAL8250
 	help
 	  MSI MS-6178 mainboard.
 endchoice
@@ -39,3 +40,18 @@ 
 	default msi/ms6178
 	depends on BOARD_MSI_MS6178
 
+config MAINBOARD_VENDOR
+	string
+	default "MSI"
+	depends on BOARD_MSI_MS6178
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MS-6178"
+	depends on BOARD_MSI_MS6178
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_MSI_MS6178
+
Index: src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- src/mainboard/msi/ms6178/devicetree.cb	(Revision 4561)
+++ src/mainboard/msi/ms6178/devicetree.cb	(Arbeitskopie)
@@ -1,3 +1,23 @@ 
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
 chip northbridge/intel/i82810			# Northbridge
   device apic_cluster 0 on			# APIC cluster
     chip cpu/intel/socket_PGA370		# CPU
@@ -6,11 +26,9 @@ 
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      #   register "rom_address" = "0xfff80000"
-      # end
+    chip drivers/pci/onboard			# Onboard VGA
+      device pci 1.0 on end
+      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
@@ -43,7 +61,7 @@ 
             irq 0x70 = 1			# Keyboard interrupt
             irq 0x72 = 12			# Mouse interrupt
           end
-          device pnp 2e.6 on end		# Consumer IR (TODO)
+          device pnp 2e.6 off end		# Consumer IR (TODO)
           device pnp 2e.7 on			# Game port / MIDI / GPIO 1
             io 0x60 = 0x201
             io 0x62 = 0x330
Index: src/mainboard/msi/ms6178/Makefile.inc
===================================================================
--- src/mainboard/msi/ms6178/Makefile.inc	(Revision 4561)
+++ src/mainboard/msi/ms6178/Makefile.inc	(Arbeitskopie)
@@ -18,36 +18,30 @@ 
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-driver-y += mainboard.o
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/cpu_reset.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
 
+obj-y += mainboard.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+
 obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
 obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
 
-initobj-y += ../../../arch/i386/init/entry.o
-initobj-y += ../../../cpu/intel/model_6ex/car.o # FIXME. romcc.
-# initobj-y += ../../../arch/i386/init/rombootstrap.o
-# initobj-y += ../../../cpu/intel/model_6ex/disable_car.o
-initobj-y += ../../../pc80/mc146818rtc_early.o
-initobj-y += ../../../arch/i386/lib/console.o
-initobj-y += ../../../arch/i386/lib/console_printk.o
-# initobj-y += ../../../ram/ramtest.o # FIXME
-initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_early_smbus.o
-initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_reset.o
-initobj-y += ../../../superio/winbond/w83627hf/w83627hf_early_serial.o
-initobj-y += ../../../northbridge/intel/i82810/raminit.o
-
 ifdef POST_EVALUATION
-
-# FIXME: Drop DCACHE_RAM_BASE/DCACHE_RAM_SIZE, only here to make it build.
-MAINBOARD_OPTIONS=\
-	-DCONFIG_USE_PRINTK_IN_CAR=1 \
-	-DCONFIG_HAVE_HIGH_TABLES=1 \
-	-DCONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0 \
-	-DCONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0 \
-	-DCONFIG_MAINBOARD_VENDOR=\"MSI\" \
-	-DCONFIG_MAINBOARD_PART_NUMBER=\"MS-6178\" \
-	-DCONFIG_DCACHE_RAM_BASE=0xffdf8000 \
-	-DCONFIG_DCACHE_RAM_SIZE=0x8000
-
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c
+	$(obj)/romcc -mcpu=p2 -O $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
 endif
 
Index: src/arch/i386/Makefile.inc
===================================================================
--- src/arch/i386/Makefile.inc	(Revision 4561)
+++ src/arch/i386/Makefile.inc	(Arbeitskopie)
@@ -5,7 +5,7 @@ 
 subdirs-y += lib
 subdirs-y += smp
 
-obj-y += ../../option_table.o
+obj-$(CONFIG_HAVE_OPTION_TABLE) += ../../option_table.o
 
 ifdef POST_EVALUATION
 BOOTBLOCK_SIZE=65536