Patchwork [inteltool] Add support for NM10 and ICH8

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Submitter Corey Osgood
Date 2010-07-30 00:22:30
Message ID <AANLkTi=ObNkzajZOXF1xQp6e+jvyOG3dR3=VorG64SKL@mail.gmail.com>
Download mbox | patch
Permalink /patch/1701/
State Accepted, archived
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Comments

Corey Osgood - 2010-07-30 00:22:30
Patch attached.

-Corey
Corey Osgood - 2010-08-04 07:48:53
Ping?

On Thu, Jul 29, 2010 at 8:22 PM, Corey Osgood <corey.osgood@gmail.com> wrote:
> Patch attached.
>
> -Corey
>
Paul Menzel - 2010-08-04 09:21:57
Dear Corey,


Am Donnerstag, den 29.07.2010, 20:22 -0400 schrieb Corey Osgood:
> Add support for the Intel NM10 (a variant of ICH7) and ICH8
> southbridges.
> Both are tested and appear to be working, however I'm not 100% clear
> on if the NM10 has any other PCI IDs.

Sorry, I cannot answer that. Although it looks like you could take a
look at the IDs in flashrom. A search for the ID turned up [1].

> Signed-off-by: Corey Osgood <corey.osgood@gmail.com> 

Looks good to me. (Although I would really like links to the data sheets
in the commit message as in [1].)

Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>

[…]


Thanks,

Paul


[1] http://www.flashrom.org/pipermail/flashrom/2010-January/001817.html
Corey Osgood - 2010-08-05 07:23:15
On Wed, Aug 4, 2010 at 5:21 AM, Paul Menzel
<paulepanter@users.sourceforge.net> wrote:
> Dear Corey,
>
>
> Am Donnerstag, den 29.07.2010, 20:22 -0400 schrieb Corey Osgood:
>> Add support for the Intel NM10 (a variant of ICH7) and ICH8
>> southbridges.
>> Both are tested and appear to be working, however I'm not 100% clear
>> on if the NM10 has any other PCI IDs.
>
> Sorry, I cannot answer that. Although it looks like you could take a
> look at the IDs in flashrom. A search for the ID turned up [1].

Yeah, the datasheet says to check the ICH7 spec update for PCI IDs,
but they're not there.

>
>> Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
>
> Looks good to me. (Although I would really like links to the data sheets
> in the commit message as in [1].)
>
> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>

Thanks, will do.

>
> […]
>
>
> Thanks,
>
> Paul
>
>
> [1] http://www.flashrom.org/pipermail/flashrom/2010-January/001817.html
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Patch

Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>


Index: gpio.c
===================================================================
--- gpio.c	(revision 5673)
+++ gpio.c	(working copy)
@@ -171,6 +171,7 @@ 
 		gpio_registers = ich9_gpio_registers;
 		size = ARRAY_SIZE(ich9_gpio_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH8:
 	case PCI_DEVICE_ID_INTEL_ICH8M:
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
 		gpio_registers = ich8_gpio_registers;
@@ -180,6 +181,7 @@ 
 	case PCI_DEVICE_ID_INTEL_ICH7M:
 	case PCI_DEVICE_ID_INTEL_ICH7DH:
 	case PCI_DEVICE_ID_INTEL_ICH7MDH:
+	case PCI_DEVICE_ID_INTEL_NM10:
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
 		gpio_registers = ich7_gpio_registers;
 		size = ARRAY_SIZE(ich7_gpio_registers);
Index: inteltool.h
===================================================================
--- inteltool.h	(revision 5673)
+++ inteltool.h	(working copy)
@@ -43,6 +43,8 @@ 
 #define PCI_DEVICE_ID_INTEL_ICH7		0x27b8
 #define PCI_DEVICE_ID_INTEL_ICH7M		0x27b9
 #define PCI_DEVICE_ID_INTEL_ICH7MDH		0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10		0x27bc
+#define PCI_DEVICE_ID_INTEL_ICH8		0x2810
 #define PCI_DEVICE_ID_INTEL_ICH8M		0x2815
 #define PCI_DEVICE_ID_INTEL_ICH9DH		0x2912
 #define PCI_DEVICE_ID_INTEL_ICH9DO		0x2914
Index: powermgt.c
===================================================================
--- powermgt.c	(revision 5673)
+++ powermgt.c	(working copy)
@@ -477,6 +477,7 @@ 
 	case PCI_DEVICE_ID_INTEL_ICH7M:
 	case PCI_DEVICE_ID_INTEL_ICH7DH:
 	case PCI_DEVICE_ID_INTEL_ICH7MDH:
+	case PCI_DEVICE_ID_INTEL_NM10:
 		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
 		pm_registers = ich7_pm_registers;
 		size = ARRAY_SIZE(ich7_pm_registers);
@@ -491,6 +492,7 @@ 
 		pm_registers = ich9_pm_registers;
 		size = ARRAY_SIZE(ich9_pm_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH8:
 	case PCI_DEVICE_ID_INTEL_ICH8M:
 		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
 		pm_registers = ich8_pm_registers;
Index: rootcmplx.c
===================================================================
--- rootcmplx.c	(revision 5673)
+++ rootcmplx.c	(working copy)
@@ -43,6 +43,8 @@ 
 	case PCI_DEVICE_ID_INTEL_ICH9M:
 	case PCI_DEVICE_ID_INTEL_ICH9ME:
 	case PCI_DEVICE_ID_INTEL_ICH8M:
+	case PCI_DEVICE_ID_INTEL_ICH8:
+	case PCI_DEVICE_ID_INTEL_NM10:
 		rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 		break;
 	case PCI_DEVICE_ID_INTEL_ICH:
Index: inteltool.c
===================================================================
--- inteltool.c	(revision 5673)
+++ inteltool.c	(working copy)
@@ -60,6 +60,8 @@ 
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },