Patchwork coreboot halts at "doing early_mtrr"

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Submitter Corey Osgood
Date 2010-08-01 03:10:51
Message ID <AANLkTikW=GyFjUvFoGY-Pc1CpDG0eSa_2YFSnX=-p622@mail.gmail.com>
Download mbox | patch
Permalink /patch/1706/
State Accepted
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Comments

Corey Osgood - 2010-08-01 03:10:51
Patch attached to remove the call to early_mtrr_init(), provide a
little more feedback on the amount of ram that's been found, and
correct the ram initialization order and clarify a comment on an old
hack. I don't have any hardware to test this patch on.

On Sat, Jul 31, 2010 at 1:33 AM, Patrick Georgi <patrick@georgi-clan.de> wrote:
> Am 30.07.2010 23:20, schrieb austinro@msu.edu:
>> Commenting out the call to early_mtrr_init() lets coreboot run to
>> completion.
> I suspect that call is a left-over from pre-CAR times on C7.
>
> Please provide a patch. See
> http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for
> our rules.
>
> Do you need any more changes to get your board to run? After all, that's
> a different board than listed by coreboot - it would be nice to support
> your board explicitely, too.
>
>> That's odd.  I assumed the call to "write_cr0(cr0)" in cache.h was
>> responsible somehow, since that was where it stopped when
>> "early_mtrr_init" called "disable_cache", but I left the print
>> statements in disable_cache, and they were all printed repeatedly this
>> time, so "write_cr0" only causes a problem when called early (during
>> "early_mtrr_init")?
> The problem is that write_cr0 is the function that actually disables the
> cache.
> While in early_mtrr_init, the only memory coreboot has to work in _is_
> the cache (Cache as RAM configures the CPU to map the cache to some RAM
> addresses and locks it to prevent eviction).
> If you disable the cache at this point, there's no memory to use. In
> particular, the stack is gone, so the next time a function is called or
> left, the CPU doesn't know where to go.
>
> On later occassions of disable_cache(), RAM is configured and used, so
> disabling the cache merely slows the system down a bit, but doesn't
> entirely prevent it from working.
>
>> Tried it again and with memtest as the payload and it doesn't see any
>> memory.  Memtest pops up on the screen :
>> L1 cache: 64K
>> L2 cache: 128K
>> L3 cache: none
>> Memory :    0K
>> (That last one is a zero K).
>>
>> Hmmm.
> This might be a matter of issues with the various tables. The fact that
> you can run up to memtest indicates that there _is_ RAM. :-)
>
> For testing you could try to disable HAVE_HIGH_TABLES - if memtest works
> then, your memtest doesn't know the forwarder entry we introduced last
> year or so.
>
>
> Patrick
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Patch

Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(revision 5674)
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(working copy)
@@ -61,8 +61,10 @@ 
 
 	PRINT_DEBUG("Waiting until SMBus ready\n");
 
-	/* Yes, this is a mess, but it's the easiest way to do it. */
-	/* XXX not so messy, but an explanation of the hack would have been better */
+	/* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the
+	 * SMBus Host Status register to go to 0, indicating the operation
+	 * was completed successfully. I don't remember why I did it this way,
+	 * but I think it was because ROMCC was running low on registers */
 	loops = 0;
 	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
 		++loops;
Index: src/mainboard/jetway/j7f24/romstage.c
===================================================================
--- src/mainboard/jetway/j7f24/romstage.c	(revision 5674)
+++ src/mainboard/jetway/j7f24/romstage.c	(working copy)
@@ -99,11 +99,6 @@ 
 	enable_smbus();
 	smbus_fixup(&ctrl);
 
-	if (bist == 0) {
-		print_debug("doing early_mtrr\n");
-		early_mtrr_init();
-	}
-
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
Index: src/northbridge/via/cn700/raminit.c
===================================================================
--- src/northbridge/via/cn700/raminit.c	(revision 5674)
+++ src/northbridge/via/cn700/raminit.c	(working copy)
@@ -183,6 +183,8 @@ 
 
 	if (result == 0xff)
 		die("DRAM module size too big, not supported by CN700\n");
+	else
+		printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
 
 	pci_write_config8(ctrl->d0f3, 0x40, result);
 	pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -400,18 +402,18 @@ 
 	read32(rank_address + 0x10);
 
 	/* 3. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
+	PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
 	do_ram_command(dev, RAM_COMMAND_MRS);
 	read32(rank_address + 0x120000);	/* EMRS DLL Enable */
 	read32(rank_address + 0x800);		/* MRS DLL Reset */
 
 	/* 4. Precharge all again. */
-	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
+	PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
 	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 	read32(rank_address + 0x0);
 
 	/* 5. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
+	PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
 	do_ram_command(dev, RAM_COMMAND_CBR);
 	for (i = 0; i < 8; i++) {
 		read32(rank_address + 0x20);
@@ -419,7 +421,7 @@ 
 	}
 
 	/* 6. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
+	PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n");
 	/* Safe value for now, BL=8, WR=5, CAS=4 */
 	/*
 	 * (E)MRS values are from the BPG. No direct explanation is given, but
@@ -432,7 +434,7 @@ 
 	read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
 
 	/* 8. Normal operation */
-	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
+	PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
 	do_ram_command(dev, RAM_COMMAND_NORMAL);
 	read32(rank_address + 0x30);
 }
Index: src/northbridge/via/cn700/northbridge.c
===================================================================
--- src/northbridge/via/cn700/northbridge.c	(revision 5674)
+++ src/northbridge/via/cn700/northbridge.c	(working copy)
@@ -177,7 +177,7 @@ 
 		}
 
 		tomk = rambits * 64 * 1024;
-		printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk);
+		printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {