| Submitter | Bao, Zheng |
|---|---|
| Date | 2010-08-02 04:54:34 |
| Message ID | <DD1CC71B621B004FA76856E5129D6B1703F86D10@sbjgexmb1.amd.com> |
| Download | mbox | patch |
| Permalink | /patch/1710/ |
| State | Accepted |
| Headers | show |
Comments
On Sun, Aug 1, 2010 at 10:54 PM, Bao, Zheng <Zheng.Bao@amd.com> wrote: > The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8]. > The bit 15 seems to be a new feature when CPU started to have more that > 4 > cores. > > Signed-off-by: Zheng Bao <zheng.bao@amd.com> Yes, this was added for revD Acked-by: Marc Jones <marcj303@gmail.com>
Patch
Index: src/northbridge/amd/amdht/h3ncmn.c =================================================================== --- src/northbridge/amd/amdht/h3ncmn.c (revision 5679) +++ src/northbridge/amd/amdht/h3ncmn.c (working copy) @@ -555,16 +555,17 @@ u8 i; ASSERT((node < nb->maxNodes)); - /* Read CmpCap */ + /* Read CmpCap [2][1:0] */ AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_CAPABILITY_3XE8), - 13, 12, &temp); + 15, 12, &temp); + /* bit[15,13,12] composes the cores */ /* Support Downcoring */ - cores = temp + 1; + cores = ((temp & 8) >> 1) + (temp & 3) + 1; AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node),
The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8]. The bit 15 seems to be a new feature when CPU started to have more that 4 cores. Signed-off-by: Zheng Bao <zheng.bao@amd.com>