Patchwork DL145 G1 with dual dualcore CPU using coreboot ?

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Submitter Oskar Enoksson
Date 2010-08-16 18:39:50
Message ID <4C6985F6.2050303@lysator.liu.se>
Download mbox | patch
Permalink /patch/1751/
State Superseded
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Comments

Oskar Enoksson - 2010-08-16 18:39:50
Ok I have made some progress: I finally tweaked mptable.c and
devicetree.cb so that all peripherals work: The two ethernet NIC's, the
Myrinet PCI-X card, IDE, USB and keyboard. Even the ILO (IPMI) card
works fine with the ipmi driver in Linux 2.6.33.

I don't know why lspci reports that all IRQ pins have been routed to IRQ
0 though (?):
[root@cl199 ~]# lspci -b -vvv | grep IRQ
        Interrupt: pin ? routed to IRQ 255
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin A routed to IRQ 0
        Interrupt: pin A routed to IRQ 0
        Interrupt: pin B routed to IRQ 0
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin A routed to IRQ 0

with the factory BIOS is looks like this:
[root@cl001 ~]# lspci -b -vvv | grep IRQ
        Interrupt: pin ? routed to IRQ 255
        Interrupt: pin D routed to IRQ 10
        Interrupt: pin D routed to IRQ 10
        Interrupt: pin A routed to IRQ 11
        Interrupt: pin A routed to IRQ 10
        Interrupt: pin B routed to IRQ 11
        Interrupt: pin A routed to IRQ 9

ACPI doesn't work (yet), but it just worked partially with the factory
BIOS anyway. The SMBus and I2C devices work (they never worked with the
factory BIOS).

The memory problem remains though. If only that can be solved, then I'm
basically satisfied. Any hints?
> Have you tried different configurations?  Coreboot is only seeing the RAM on
> node 0.  Where is the RAM on your board?
>   
I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
not. If I move all four DIMM's to CPU0 then coreboot detects 2GB but
hangs when initializing the memory. The same thing happens if I use two
1GB DIMM's.

Something is wrong with the way memory is detected on the second CPU,
that's for sure. This is from dmesg:

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
 BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000003ffef000 (usable)
 BIOS-e820: 000000003ffef000 - 0000000040000000 (reserved)
...
EDAC MC: Ver: 2.1.0 Aug 11 2010
EDAC amd64_edac:  Ver: 3.3.0 Aug 11 2010
EDAC amd64: ECC is enabled by BIOS.
EDAC amd64: This node reports that Memory ECC is currently disabled, set
F3x44[22] (0000:00:19.3).
EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will
not load.
 Either enable ECC checking or force module loading by setting
'ecc_enable_override'.
 (Note that use of the override may cause unknown side effects.)
amd64_edac: probe of 0000:00:19.2 failed with error -22
EDAC MC: Rev E or earlier detected
EDAC MC0: Giving out device to 'amd64_edac' 'RevF': DEV 0000:00:18.2
EDAC PCI0: Giving out device to module 'amd64_edac' controller 'EDAC PCI
controller': DEV '0000:00:18.2' (POLLED)


The output from "svn diff src/mainboard" is in attachment 1
The console output "SPEW" level from coreboot is in attachment 2

Thanks.
Myles Watson - 2010-08-16 19:15:21
> Ok I have made some progress: I finally tweaked mptable.c and
> devicetree.cb so that all peripherals work: The two ethernet NIC's, the
> Myrinet PCI-X card, IDE, USB and keyboard. Even the ILO (IPMI) card
> works fine with the ipmi driver in Linux 2.6.33.
Congratulations.

> I don't know why lspci reports that all IRQ pins have been routed to IRQ
> 0 though (?):
I don't know where lspci gets its values.  It could be interesting to track
it down, but if it works...

> ACPI doesn't work (yet), but it just worked partially with the factory
> BIOS anyway. The SMBus and I2C devices work (they never worked with the
> factory BIOS).
> 
> The memory problem remains though. If only that can be solved, then I'm
> basically satisfied. Any hints?
> > Have you tried different configurations?  Coreboot is only seeing the
> RAM on
> > node 0.  Where is the RAM on your board?
> >
> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
> not.
It's possible that there is a mux in the way that needs to be set up
correctly to allow you to read the DIMMs on the other CPU.

> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
> hangs when initializing the memory.
That sounds like a different problem.  Maybe the mux idea isn't right.

> The same thing happens if I use two
> 1GB DIMM's.
I'd start by enabling the debugging output CONFIG_DEBUG_SMBUS.  I haven't
had to dig very much in that part of the code.

Thanks,
Myles
Myles Watson - 2010-08-16 19:23:08
I forgot DEBUG_RAM_SETUP. 

Thanks,
Myles
Carl-Daniel Hailfinger - 2010-08-17 04:05:34
On 16.08.2010 21:15, Myles Watson wrote:
>> The memory problem remains though. If only that can be solved, then I'm
>> basically satisfied. Any hints?
>>
>>     
>>> Have you tried different configurations?  Coreboot is only seeing the
>>> RAM on node 0.  Where is the RAM on your board?
>>>       
>> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
>> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
>> not.
>>     
>
> It's possible that there is a mux in the way that needs to be set up
> correctly to allow you to read the DIMMs on the other CPU.
>   
>> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
>> hangs when initializing the memory.
>>     
> That sounds like a different problem.  Maybe the mux idea isn't right.
>   

Very odd. Enabling DRAM debugging is a good idea.
By the way, please check if the SPDs for all DIMMs match. If the DIMMs
are just compatible and not identical, coreboot may have problems
detecting all RAM. OTOH, if all visible (from a SPD perspective) DIMMs
are also present in the computed memory count, your problem is unrelated
to what I suggested.

Regards,
Carl-Daniel
Oskar Enoksson - 2010-08-17 12:52:15
Carl-Daniel Hailfinger wrote:
> On 16.08.2010 21:15, Myles Watson wrote:
>   
>>> The memory problem remains though. If only that can be solved, then I'm
>>> basically satisfied. Any hints?
>>>
>>>     
>>>       
>>>> Have you tried different configurations?  Coreboot is only seeing the
>>>> RAM on node 0.  Where is the RAM on your board?
>>>>       
>>>>         
>>> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
>>> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
>>> not.
>>>     
>>>       
>> It's possible that there is a mux in the way that needs to be set up
>> correctly to allow you to read the DIMMs on the other CPU.
>>   
>>     
>>> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
>>> hangs when initializing the memory.
>>>     
>>>       
>> That sounds like a different problem.  Maybe the mux idea isn't right.
>>   
>>     
>
> Very odd. Enabling DRAM debugging is a good idea.
> By the way, please check if the SPDs for all DIMMs match. If the DIMMs
> are just compatible and not identical, coreboot may have problems
> detecting all RAM. OTOH, if all visible (from a SPD perspective) DIMMs
> are also present in the computed memory count, your problem is unrelated
> to what I suggested.
>
> Regards,
> Carl-Daniel
>   
I think Myles was right, there is a i2c mux in this server that somehow
multiplexes DIMM devices on the i2c bus. I was able to guess which i2c
ports contain the DIMM info, and which port is the mux, then added the
mux to devicetree.cb and the DIMM ports under it. Now I'm able to use
memory from both CPU's, at least for the combination of DIMM's I have
(2x2x1GB and 2x2x512MB).

So I'm basically able to use these servers now. I would love to have
ACPI and Cool'nQuiet of course, perhaps I'll try to do that later.

Thanks very much for all help! If you want me to commit the new
mainboard to your svn repository let me know.

Best regards.
/Oskar
Myles Watson - 2010-08-17 16:26:41
> I think Myles was right, there is a i2c mux in this server that somehow
> multiplexes DIMM devices on the i2c bus. I was able to guess which i2c
> ports contain the DIMM info, and which port is the mux, then added the
> mux to devicetree.cb and the DIMM ports under it. Now I'm able to use
> memory from both CPU's, at least for the combination of DIMM's I have
> (2x2x1GB and 2x2x512MB).
I'm glad it worked out!

> So I'm basically able to use these servers now. I would love to have
> ACPI and Cool'nQuiet of course, perhaps I'll try to do that later.
> 
> Thanks very much for all help! If you want me to commit the new
> mainboard to your svn repository let me know.
Yes, please.  If you'll send your latest patch with a Signed-off-by: line,
I'll take it from there.

Thanks,
Myles
Myles Watson - 2010-08-20 14:42:41
On Fri, Aug 20, 2010 at 8:32 AM, Oskar Enoksson <enok@lysator.liu.se> wrote:
> Myles Watson wrote:
>>> I'll send the updated patch when I'm at the office in the morning.
>>>
>>> I want to say also: this code should probably be regarded as
>>> experimental. I already know it doesn't boot with Opteron 248 CPU's, and
>>> sometimes it hangs on my 280 CPU's also.
>>>
>> I don't remember seeing the boot logs.  Have you compared the failing boot
>> logs with the working ones?
>>
> I think I solved a problem with the memory (mux) initialization
> (memreset and memreset_setup), now I can safely boot on both the 2x 248
> server and the 2x 280 server.
Good news.

> But I noticed that memtest86+ hangs. After some trial-and-error I
> noticed that if I use CONFIG_WRITE_HIGH_TABLES=y then everything works
> fine in Linux, but memtest86+ hangs. If I use CONFIG_WRITE_HIGH_TABLES=n
> memtest86+ works fine, but the Linux kernel fails to initialize the
> ethernet NIC's. What could be wrong?
My guess is that memtest doesn't like the reserved area in the middle
of RAM, but I don't know for sure.

> The original BIOS reports this memory map:
>  BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
>  BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
>  BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
>  BIOS-e820: 0000000000100000 - 00000000f9ff0000 (usable)
>  BIOS-e820: 00000000f9ff0000 - 00000000f9fff000 (ACPI data)
>  BIOS-e820: 00000000f9fff000 - 00000000fa000000 (ACPI NVS)
>  BIOS-e820: 00000000ffb80000 - 0000000100000000 (reserved)
>
> My coreboot reports:
>  BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
>  BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
>  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
>  BIOS-e820: 0000000000100000 - 000000007fff0000 (usable)
>  BIOS-e820: 000000007fff0000 - 0000000080000000 (reserved)
>  BIOS-e820: 0000000080000000 - 00000000f7fff000 (usable)
>  BIOS-e820: 00000000f7fff000 - 00000000f8000000 (reserved)
>
> Is there something that looks wrong with the coreboot table?
I'm surprised that the high tables ended up in the middle of RAM.  I'd
reccommend looking through the log to see why that area gets reserved
there (is it reserved twice?)

>One more
> oddity that could be related: when booting with coreboot and then
> running flashrom I always get an error like this:
>
> flashrom is free software, get the source code at http://www.flashrom.org
> Error accessing high tables, 0x100000 bytes at 0x7fff2000
Odd that it wants to acess 1M of high tables at an unaligned address.

> /dev/mem mmap failed: Invalid argument
> In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),
> CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.
> Please check if either is enabled in your kernel before reporting a failure.
> You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but
> disabling the other option unfortunately requires a kernel recompile. Sorry!
> Failed getting access to coreboot high tables.
> Found chipset "AMD AMD8111", enabling flash write... OK.
> This chipset supports the following protocols: Non-SPI.
> Calibrating delay loop... delay loop is unreliable, trying to continue OK.
> Found chip "SST SST49LF040" (512 KB, LPC) at physical address 0xfff80000.
>
> It works though and I can write to the flash. With the factory BIOS
> there are no error messages:
>
> flashrom is free software, get the source code at http://www.flashrom.org
> No coreboot table found.
> Found chipset "AMD AMD8111", enabling flash write... OK.
> This chipset supports the following protocols: Non-SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST49LF040" (512 KB, LPC) at physical address 0xfff80000.

Using the mailing list will generally get you a better response and
help others later.

Thanks,
Myles

Patch

Index: src/mainboard/hp/Kconfig
===================================================================
--- src/mainboard/hp/Kconfig	(revision 5689)
+++ src/mainboard/hp/Kconfig	(working copy)
@@ -2,6 +2,7 @@ 
 	prompt "Mainboard model"
 	depends on VENDOR_HP
 
+source "src/mainboard/hp/dl145_g1/Kconfig"
 source "src/mainboard/hp/dl145_g3/Kconfig"
 source "src/mainboard/hp/e_vectra_p2706t/Kconfig"
 
Index: src/mainboard/hp/dl145_g1/Kconfig
===================================================================
--- src/mainboard/hp/dl145_g1/Kconfig	(revision 5689)
+++ src/mainboard/hp/dl145_g1/Kconfig	(working copy)
@@ -1,5 +1,5 @@ 
-config BOARD_TYAN_S2881
-	bool "S2881 (Thunder K8SR)"
+config BOARD_HP_DL145_G1
+	bool "ProLiant DL145 G1"
 	select ARCH_X86
 	select CPU_AMD_SOCKET_940
 	select NORTHBRIDGE_AMD_AMDK8
@@ -13,65 +13,77 @@ 
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select DRIVERS_SIL
 
+#	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
 config MAINBOARD_DIR
 	string
-	default tyan/s2881
-	depends on BOARD_TYAN_S2881
+	default hp/dl145_g1
+	depends on BOARD_HP_DL145_G1
 
 config APIC_ID_OFFSET
 	hex
 	default 0x0
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "S2881"
-	depends on BOARD_TYAN_S2881
+	default "ProLiant DL145 G1"
+	depends on BOARD_HP_DL145_G1
 
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_HP_DL145_G1
+
+#config TTYS0_LCS
+#	hex
+#	default 0x3
+#	depends on BOARD_HP_DL145_G1
+
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
-	default 0x2881
-	depends on BOARD_TYAN_S2881
+	default 0x1451
+	depends on BOARD_HP_DL145_G1
 
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAX_CPUS
 	int
 	default 4
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAX_PHYSICAL_CPUS
 	int
 	default 2
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config HT_CHAIN_UNITID_BASE
 	hex
-	default 0xa
-	depends on BOARD_TYAN_S2881
+#	default 0xa
+	default 0x1
+	depends on BOARD_HP_DL145_G1
 
 config HT_CHAIN_END_UNITID_BASE
 	hex
 	default 0x6
-	depends on BOARD_TYAN_S2881
+#	default 0x20
+	depends on BOARD_HP_DL145_G1
 
 config IRQ_SLOT_COUNT
 	int
-	default 9
-	depends on BOARD_TYAN_S2881
+	default 12
+	depends on BOARD_HP_DL145_G1
Index: src/mainboard/hp/dl145_g1/devicetree.cb
===================================================================
--- src/mainboard/hp/dl145_g1/devicetree.cb	(revision 5689)
+++ src/mainboard/hp/dl145_g1/devicetree.cb	(working copy)
@@ -1,82 +1,67 @@ 
 chip northbridge/amd/amdk8/root_complex
-        device lapic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device lapic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on
-                                                device pci 9.0 on end # Broadcom 5704
-                                                device pci 9.1 on end
-                                                device pci a.0 on end # Adaptic
-                                                device pci a.1 on end
-					end
-					device pci 0.1 on end
+        device pci_domain 0 on
+                chip northbridge/amd/amdk8 # mc
+                        device pci 18.0 on end # LDT0
+                        device pci 18.0 on end # LDT1
+                        device pci 18.0 on     # LDT2
+                                chip southbridge/amd/amd8131
+                                        # the on/off keyword is mandatory
+					device pci 0.0 on end
+                                        device pci 0.1 on end
 					device pci 1.0 on end
 					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 5.0 on end # SiI
-                                                device pci 6.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
+					device pci 2.0 on end
+					device pci 2.1 on end
+					device pci 3.0 off end
+                                end
+                                chip southbridge/amd/amd8111
+                                        # this "device pci 0.0" is the parent the next one
+                                        # PCI bridge
+                                        device pci 0.0 on
+                                                device pci 0.0 on end  # LPC
+                                                device pci 0.1 on end  # IDE
+                                                device pci 0.2 on end  # SMbus
+                                                device pci 0.3 on end  # ACPI
+                                                device pci 1.0 off end
+                                        end
+                                        device pci 1.0 on
+                                                chip superio/winbond/w83627hf
+                                                        device pnp 2e.0 on  # Floppy
+                                                                io  0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off  # Parallel Port
+                                                                io  0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 on # Com 1
+                                                                io  0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.3 off # Com 2
+                                                                io  0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.5 on  # Keyboard
+                                                                io  0x60 = 0x60
+                                                                io  0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                        device pnp 2e.6 off end # CIR
+                                                        device pnp 2e.7 off end # GAM_MIDI_GIPO1
+                                                        device pnp 2e.8 off end # GPIO2
+                                                        device pnp 2e.9 off end # GPIO3
+                                                        device pnp 2e.a on  end # ACPI
+                                                        device pnp 2e.b on      # HW Monitor
+                                                                io  0x60 = 0x290
                 	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
+                                                       end
+                                                end
+                                        end
+                                        device pci 1.1 on end
+                                        device pci 1.2 on end
                                         device pci 1.3 on
                                                 chip drivers/generic/generic #dimm 0-0-0
                                                         device i2c 50 on end
@@ -115,17 +100,33 @@ 
                                                         device i2c 4a on end
                                                 end
                                         end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
+                                        device pci 1.5 off end
+                                        device pci 1.6 off end
                                         register "ide0_enable" = "1"
                                         register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end
+                                end
+                        end # device pci 18.0
+                       
+                        device pci 18.1 on end
+                        device pci 18.2 on end
+                        device pci 18.3 on end
+                end
+                chip northbridge/amd/amdk8
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.1 on end
+                        device pci 19.2 on end
+                        device pci 19.3 on end
+                end
+        end
+        device lapic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device lapic 0 on end
+                end
+                chip cpu/amd/socket_940
+                        device lapic 1 on end
+                end
+        end
 end
 
Index: src/mainboard/hp/dl145_g1/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g1/romstage.c	(revision 5689)
+++ src/mainboard/hp/dl145_g1/romstage.c	(working copy)
@@ -123,7 +123,8 @@ 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        setup_s2881_resource_map();
+        setup_dl145g1_resource_map();
+        //setup_default_resource_map();
 #if 0
         dump_pci_device(PCI_DEV(0, 0x18, 0));
 	dump_pci_device(PCI_DEV(0, 0x19, 0));
Index: src/mainboard/hp/dl145_g1/mptable.c
===================================================================
--- src/mainboard/hp/dl145_g1/mptable.c	(revision 5689)
+++ src/mainboard/hp/dl145_g1/mptable.c	(working copy)
@@ -23,8 +23,8 @@ 
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "COREBOOT";
-        static const char productid[12] = "S2881       ";
+        static const char oem[8] = "FOI     ";
+        static const char productid[12] = "DL145G1     ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;
@@ -62,7 +62,7 @@ 
 
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+	smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
         {
                 device_t dev;
                 struct resource *res;
@@ -70,14 +70,14 @@ 
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+                                smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
                         }
                 }
                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+                                smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
                         }
                 }
 
@@ -86,42 +86,26 @@ 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
 
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-//8111 LPC ????
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
+	// Integrated SMBus 2.0
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111  , 0x13);
+	// Integrated AMD AC97 Audio
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111  , 0x11);
+	// Integrated AMD USB
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111  , 0x12);
+	// On board ATI Rage XL
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111  , 0x10);
+	// On board Broadcom nics
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+	// On board LSI SCSI
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
 
-//On Board AMD USB ???
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
+	// PCIX Slot
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x4);
 
-//On Board ATI Display Adapter
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
-
-//On Board SI Serial ATA
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
-
-//Slot 3 PCIX 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
-        }
-
-//On Board NIC and adaptec scsi
-        for(i=0;i<2;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
-        }
-
-//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
-        }
-
-        //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
-        //Fix ME, IRQ Pins?
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
-        }
-
-
-
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
Index: src/mainboard/hp/dl145_g1/irq_tables.c
===================================================================
--- src/mainboard/hp/dl145_g1/irq_tables.c	(revision 5689)
+++ src/mainboard/hp/dl145_g1/irq_tables.c	(working copy)
@@ -51,7 +51,7 @@ 
         uint8_t sum=0;
         int i;
 
-	get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and acpi_tables.c
 
         /* Align the table to be 16 byte aligned. */
         addr += 15;
Index: src/mainboard/hp/dl145_g1/resourcemap.c
===================================================================
--- src/mainboard/hp/dl145_g1/resourcemap.c	(revision 5689)
+++ src/mainboard/hp/dl145_g1/resourcemap.c	(working copy)
@@ -1,9 +1,9 @@ 
 /*
- * Tyan S2881 needs a different resource map
+ * DL145G1 needs a different resource map
  *
  */
 
-static void setup_s2881_resource_map(void)
+static void setup_dl145g1_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 	/* Careful set limit registers before base registers which contain the enables */
Index: src/mainboard/hp/dl145_g1/mainboard.c
===================================================================
--- src/mainboard/hp/dl145_g1/mainboard.c	(revision 5689)
+++ src/mainboard/hp/dl145_g1/mainboard.c	(working copy)
@@ -24,5 +24,5 @@ 
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("Tyan S2881 Mainboard")
+	CHIP_NAME("HP DL145G1 Mainboard")
 };