ht init and some errata for AMD fam 10 RB_C3

Submitter	xdrudis
Date	2010-08-17 06:44:10
Message ID	<20100817064410.GB4296@ideafix.casa.ct>
Download	mbox \| patch
Permalink	/patch/1760/
State	Superseded
Headers	show Return-path: <coreboot-bounces@coreboot.org> Envelope-to: patchwork@coreboot.org Date: Tue, 17 Aug 2010 08:44:10 +0200 To: coreboot@coreboot.org Message-ID: <20100817064410.GB4296@ideafix.casa.ct> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="1LKvkjL3sHcu1TtY" Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) From: xdrudis <xdrudis@tinet.cat> Subject: [coreboot] [PATCH] ht init and some errata for AMD fam 10 RB_C3 Precedence: list Sender: coreboot-bounces@coreboot.org Errors-To: coreboot-bounces@coreboot.org

Comments

xdrudis - 2010-08-17 06:44:10

Hi.

This is the rest of patches to get until fidvid or staring 
ram stage, apparently at random. In fact once I've cleaned 
up the other patches a little I can't seem to make it stop at fidvid 
as it used to, but I guess with a dozen more tries it will...

It's including RB-C3 in AMD_FAM10_ALL
and adding some patches. It misses constants for new models 
that should also get some errata treatment.

It applies to 5703 with patch.warnerror, patch.serial1, and 
patch procnames, together with the new m4a77td-pro dir I haven't 
sent. 

I know I should split it to smaller pieces, I just haven't had 
the time yet, and there's some overlap, so I must take care...

Signed off by: Xavi Drudis Ferran <xdrudis@tinet.cat>

Patch

Index: src/cpu/amd/model_10xxx/defaults.h
===================================================================
--- src/cpu/amd/model_10xxx/defaults.h	(revision 5692)
+++ src/cpu/amd/model_10xxx/defaults.h	(working copy)
@@ -88,6 +88,10 @@ 
 	{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
 	  0x00000000, 1 << (33-32),
 	  0x00000000, 1 << (33-32) },	/* [ExtendedFeatEn]=1 */
+
+        { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
+	  0x00000000, 1 << (35-32),
+	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() )  */  
 };
 
 
@@ -136,28 +140,28 @@ 
 	 * program Link Global Extended Control Register[ForceFullT0]
 	 * (F0x16C[15:13]) to 000b */
 
-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
+	{ 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */
 	  0x00000000, 0x00000100 },
-	{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x174,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x178,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x17C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x180,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x184,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x188,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x18C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x170,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
 
 	/* Link Global Extended Control Register */
-	{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
-	  0x00000014, 0x0000003F },	/* [15:13] ForceFullT0 = 0b,
+	{ 0, 0x16C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
+	  0x00000014, 0x0000E03F },	/* [15:13] ForceFullT0 = 0b,
 								 * Set T0Time 14h per BKDG */
 
 
@@ -290,9 +294,9 @@ 
 					   [5] DisPciCfgCpuMstAbtRsp = 1,
 					   [1] SyncFloodOnUsPwDataErr = 1 */
 
-	/* errata 346 - Fam10 C2
+	/* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants
 	 *  System software should set F3x188[22] to 1b. */
-	{ 3, 0x188, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL,
+	{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
 	  0x00400000, 0x00400000 },
 
 	/* L3 Control Register */
@@ -317,9 +321,9 @@ 
 	u32 mask;
 } fam10_htphy_default[] = {
 
-	/* Errata 344 - Fam10 C2/D0
+	/* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them
 	 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
-	{ 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x60,   AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 	{ 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
@@ -357,44 +361,44 @@ 
 	{ 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	/* Errata 354 - Fam10 C2
+	/* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants
 	 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-	{ 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	{ 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
 	/* Errata 327 - Fam10 C2/D0
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h	(revision 5692)
+++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h	(working copy)
@@ -118,6 +118,7 @@ 
 #define TestFail		2	/* func 2, offset 40h-5C, bit 2*/
 #define DqsRcvEnTrain		18	/* func 2, offset 78h, bit 18*/
 #define EnDramInit		31	/* func 2, offset 7Ch, bit 31*/
+#define PchgPDModeSel           23      /* func 2, offset 84h, bit 23 */
 #define DisAutoRefresh		18	/* func 2, offset 8Ch, bit 18*/
 #define InitDram		0	/* func 2, offset 90h, bit 0*/
 #define BurstLength32		10	/* func 2, offset 90h, bit 10*/
@@ -128,6 +129,7 @@ 
 #define MemClkFreqVal		3	/* func 2, offset 94h, bit 3*/
 #define RDqsEn			12	/* func 2, offset 94h, bit 12*/
 #define DisDramInterface	14	/* func 2, offset 94h, bit 14*/
+#define PowerDownEn      	15	/* func 2, offset 94h, bit 15*/
 #define DctAccessWrite		30	/* func 2, offset 98h, bit 30*/
 #define DctAccessDone		31	/* func 2, offset 98h, bit 31*/
 #define MemClrStatus		0	/* func 2, offset A0h, bit 0*/
@@ -175,6 +177,7 @@ 
 #define Ddr3FourSocketCh	2	/* func 2, offset A8h, bit 2 */
 #define SendControlWord		30	/* func 2, offset 7Ch, bit 30 */
 
+#define NB_GfxNbPstateDis       62     /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */
 /*=============================================================================
 	SW Initialization
 ============================================================================*/
Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- src/northbridge/amd/amdmct/wrappers/mcti_d.c	(revision 5692)
+++ src/northbridge/amd/amdmct/wrappers/mcti_d.c	(working copy)
@@ -400,14 +400,50 @@ 
 	coreDelay();
 
 }
+ 
+
+static void vErratum372(struct DCTStatStruc *pDCTstat)
+{
+        msr_t msr = rdmsr(NB_CFG_MSR);
+  
+        int  nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ;
+
+        // is this the right way to check for NB pstate 1 or DDR3-1333 ? 
+        if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+            &&(!pDCTstat->GangedMode)) {
+           	/* DisableCf8ExtCfg */
+        	msr.hi &= ~(3 << (51 - 32));
+        	wrmsr(NB_CFG_MSR, msr);
+        }
+}
+
+static void vErratum414(struct DCTStatStruc *pDCTstat)
+{
+     int dct=0;
+    for(; dct < 2 ; dct++) 
+    {
+        int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); 
+        int powerDown =  dRAMConfigHi && (1 << PowerDownEn ) ;
+        int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ;
+        int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
+        int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ;
+	if (powerDown && ddr3 && pchgPDModeSel ) 
+	{
+	  Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
+	}
+    }
+}
 #endif
 
 
 static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 {
 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
-	if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
+  /* FIXME :  as of 25.6.2010 errata 350 and 372 should apply to  ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */
+	if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) {
 		vErrata350(pMCTstat, pDCTstatA);
+		vErratum372(pDCTstatA);
+		vErratum414(pDCTstatA);
 	}
 #endif
 }
Index: src/northbridge/amd/amdmct/amddefs.h
===================================================================
--- src/northbridge/amd/amdmct/amddefs.h	(revision 5692)
+++ src/northbridge/amd/amdmct/amddefs.h	(working copy)
@@ -62,12 +62,13 @@ 
 #define	AMD_DR_LT_B3	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2)
+#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_Cx       (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3)
 #define	AMD_DR_Dx       (AMD_HY_D0)
+#define	AMD_DRBH_Cx       (AMD_DR_Cx | AMD_HY_D0 )
+#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
 
-
 /*
  *  Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE
  */

Patchwork ht init and some errata for AMD fam 10 RB_C3

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