Patchwork include RB-C3 in workaround for erratum 354

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Submitter xdrudis
Date 2010-08-19 22:08:06
Message ID <20100819220806.GH7181@ideafix.casa.ct>
Download mbox | patch
Permalink /patch/1778/
State Accepted
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xdrudis - 2010-08-19 22:08:06
Last one, 

Signed off by: Xavi Drudis Ferran <xdrudis@tinet.cat>
RB_C3  should also apply the workaround for errata 354, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

Patch

Index: src/cpu/amd/model_10xxx/defaults.h
===================================================================
--- src/cpu/amd/model_10xxx/defaults.h	(revision 5692)
+++ src/cpu/amd/model_10xxx/defaults.h	(working copy)
@@ -361,44 +361,44 @@ 
 	{ 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	/* Errata 354 - Fam10 C2
+	/* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants
 	 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-	{ 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	{ 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },