Patchwork move PHY fine tune to devicetree.cb

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Submitter Rudolf Marek
Date 2010-08-22 20:37:53
Message ID <4C718AA1.90009@assembler.cz>
Download mbox | patch
Permalink /patch/1785/
State New
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Comments

Rudolf Marek - 2010-08-22 20:37:53
Hello,

Following patch moves the PHY fine tune settings into devicetree.cb. Suited for 
AMD SB7xx. Please change the default settings for Gigabyte and Jetway.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

Untested I can test on monday evening.

Thanks,
Rudolf
Stefan Reinauer - 2010-08-22 21:38:03
On 8/22/10 10:37 PM, Rudolf Marek wrote:
> Index: src/mainboard/amd/mahogany/devicetree.cb
> ===================================================================
> --- src/mainboard/amd/mahogany/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
> +++ src/mainboard/amd/mahogany/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
> @@ -110,6 +110,19 @@
>  					register "sata0_enable" = "1"
>  					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
>  					register "hda_viddid" = "0x10ec0882"
> +					# SATA PHY fine tune, depends on PCB layout!
> +					register "sphy15_p0" = "0x01b48017"
> +					register "sphy15_p1" = "0x01b48019"
> +					register "sphy15_p2" = "0x01b48016"
> +					register "sphy15_p3" = "0x01b48016"
> +					register "sphy15_p4" = "0x01b48016"
> +					register "sphy15_p5" = "0x01b48016"
> +					register "sphy30_p0" = "0xa09a"
> +					register "sphy30_p1" = "0xa09f"
> +					register "sphy30_p2" = "0xa07a"
> +					register "sphy30_p3" = "0xa07a"
> +					register "sphy30_p4" = "0xa07a"
> +					register "sphy30_p5" = "0xa07a"
>  				end	#southbridge/amd/sb700
>  			end #  device pci 18.0

Shouldn't such values rather go into the mainboard specific code (ie an
array in mainboard,c) instead of the device tree?
Patrick Georgi - 2010-08-22 21:41:10
Am 22.08.2010 23:38, schrieb Stefan Reinauer:
> Shouldn't such values rather go into the mainboard specific code (ie an
> array in mainboard,c) instead of the device tree?
Depends on what we define the purpose of the registers in the devicetree
to be.
Some of the things we currently stuff in registers might be better put
into CMOS ("ide or sata" decisions, for example), so that's a more
general question than just for these values.


Patrick
Carl-Daniel Hailfinger - 2010-08-22 22:24:27
On 22.08.2010 23:41, Patrick Georgi wrote:
> Am 22.08.2010 23:38, schrieb Stefan Reinauer:
>   
>> Shouldn't such values rather go into the mainboard specific code (ie an
>> array in mainboard,c) instead of the device tree?
>>     
> Depends on what we define the purpose of the registers in the devicetree
> to be.
> Some of the things we currently stuff in registers might be better put
> into CMOS ("ide or sata" decisions, for example), so that's a more
> general question than just for these values.
>   

If we don't store mainboard specific settings for generic (chipset,
superio) hardware in the device tree, what settings should be in the
device tree? None?

Regards,
Carl-Daniel
Stefan Reinauer - 2010-08-23 07:33:51
On 8/23/10 12:24 AM, Carl-Daniel Hailfinger wrote:
> On 22.08.2010 23:41, Patrick Georgi wrote:
>> Am 22.08.2010 23:38, schrieb Stefan Reinauer:
>>   
>>> Shouldn't such values rather go into the mainboard specific code (ie an
>>> array in mainboard,c) instead of the device tree?
>>>     
>> Depends on what we define the purpose of the registers in the devicetree
>> to be.
>> Some of the things we currently stuff in registers might be better put
>> into CMOS ("ide or sata" decisions, for example), so that's a more
>> general question than just for these values.
>>   
> If we don't store mainboard specific settings for generic (chipset,
> superio) hardware in the device tree, what settings should be in the
> device tree? None?
higher level information, not just register dumps.

Patch

Index: src/southbridge/amd/sb700/sb700_sata.c
===================================================================
--- src/southbridge/amd/sb700/sb700_sata.c.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/southbridge/amd/sb700/sb700_sata.c	2010-08-22 11:54:40.000000000 +0200
@@ -62,9 +62,7 @@ 
 	u32 sata_bar5;
 	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
 	int i, j;
-
-	struct southbridge_ati_sb700_config *conf;
-	conf = dev->chip_info;
+	struct southbridge_amd_sb700_config *conf = dev->chip_info;
 
 	device_t sm_dev;
 	/* SATA SMBus Disable */
@@ -167,20 +165,20 @@ 
 	pci_write_config16(dev, 0x86, word);
 
 	/* RPR7.6.2 SATA GENI PHY ports setting */
-	pci_write_config32(dev, 0x88, 0x01B48017);
-	pci_write_config32(dev, 0x8c, 0x01B48019);
-	pci_write_config32(dev, 0x90, 0x01B48016);
-	pci_write_config32(dev, 0x94, 0x01B48016);
-	pci_write_config32(dev, 0x98, 0x01B48016);
-	pci_write_config32(dev, 0x9C, 0x01B48016);
+	pci_write_config32(dev, 0x88, conf->sphy15_p0);
+	pci_write_config32(dev, 0x8c, conf->sphy15_p1);
+	pci_write_config32(dev, 0x90, conf->sphy15_p2);
+	pci_write_config32(dev, 0x94, conf->sphy15_p3);
+	pci_write_config32(dev, 0x98, conf->sphy15_p4);
+	pci_write_config32(dev, 0x9C, conf->sphy15_p5);
 
 	/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
-	pci_write_config16(dev, 0xA0, 0xA09A);
-	pci_write_config16(dev, 0xA2, 0xA09F);
-	pci_write_config16(dev, 0xA4, 0xA07A);
-	pci_write_config16(dev, 0xA6, 0xA07A);
-	pci_write_config16(dev, 0xA8, 0xA07A);
-	pci_write_config16(dev, 0xAA, 0xA07A);
+	pci_write_config16(dev, 0xA0, conf->sphy30_p0);
+	pci_write_config16(dev, 0xA2, conf->sphy30_p1);
+	pci_write_config16(dev, 0xA4, conf->sphy30_p2);
+	pci_write_config16(dev, 0xA6, conf->sphy30_p3);
+	pci_write_config16(dev, 0xA8, conf->sphy30_p4);
+	pci_write_config16(dev, 0xAA, conf->sphy30_p5);
 
 	/* Enable the I/O, MM, BusMaster access for SATA */
 	byte = pci_read_config8(dev, 0x4);
Index: src/southbridge/amd/sb700/chip.h
===================================================================
--- src/southbridge/amd/sb700/chip.h.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/southbridge/amd/sb700/chip.h	2010-08-22 12:12:45.000000000 +0200
@@ -26,6 +26,18 @@ 
 	u32 sata0_enable : 1;
 	u32 boot_switch_sata_ide : 1;
 	u32 hda_viddid;
+	u32 sphy15_p0;
+	u32 sphy15_p1;
+	u32 sphy15_p2;
+	u32 sphy15_p3;
+	u32 sphy15_p4;
+	u32 sphy15_p5;
+	u32 sphy30_p0;
+	u32 sphy30_p1;
+	u32 sphy30_p2;
+	u32 sphy30_p3;
+	u32 sphy30_p4;
+	u32 sphy30_p5;
 };
 struct chip_operations;
 extern struct chip_operations southbridge_amd_sb700_ops;
Index: src/mainboard/asrock/939a785gmh/devicetree.cb
===================================================================
--- src/mainboard/asrock/939a785gmh/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/asrock/939a785gmh/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -120,6 +120,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48016"
+					register "sphy15_p1" = "0x01b48016"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa07a"
+					register "sphy30_p1" = "0xa07a"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa0ff"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/gigabyte/ma78gm/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma78gm/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/gigabyte/ma78gm/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -101,6 +101,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/gigabyte/ma785gmt/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma785gmt/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/gigabyte/ma785gmt/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -102,6 +102,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/amd/mahogany/devicetree.cb
===================================================================
--- src/mainboard/amd/mahogany/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/mahogany/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -110,6 +110,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/amd/mahogany_fam10/devicetree.cb
===================================================================
--- src/mainboard/amd/mahogany_fam10/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/mahogany_fam10/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -101,6 +101,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/amd/tilapia_fam10/devicetree.cb
===================================================================
--- src/mainboard/amd/tilapia_fam10/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/tilapia_fam10/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
@@ -102,6 +102,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0
 
Index: src/mainboard/jetway/pa78vm5/devicetree.cb
===================================================================
--- src/mainboard/jetway/pa78vm5/devicetree.cb.orig	2010-08-22 12:13:07.000000000 +0200
+++ src/mainboard/jetway/pa78vm5/devicetree.cb	2010-08-22 12:13:16.000000000 +0200
@@ -101,6 +101,19 @@ 
 					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 					register "hda_viddid" = "0x10ec0882"
+					# SATA PHY fine tune, depends on PCB layout!
+					register "sphy15_p0" = "0x01b48017"
+					register "sphy15_p1" = "0x01b48019"
+					register "sphy15_p2" = "0x01b48016"
+					register "sphy15_p3" = "0x01b48016"
+					register "sphy15_p4" = "0x01b48016"
+					register "sphy15_p5" = "0x01b48016"
+					register "sphy30_p0" = "0xa09a"
+					register "sphy30_p1" = "0xa09f"
+					register "sphy30_p2" = "0xa07a"
+					register "sphy30_p3" = "0xa07a"
+					register "sphy30_p4" = "0xa07a"
+					register "sphy30_p5" = "0xa07a"
 				end	#southbridge/amd/sb700
 			end #  device pci 18.0