Patchwork remove unused devicetree.cb entries

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Submitter Rudolf Marek
Date 2010-08-22 20:39:35
Message ID <4C718B07.8080809@assembler.cz>
Download mbox | patch
Permalink /patch/1786/
State Accepted
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Comments

Rudolf Marek - 2010-08-22 20:39:35
Hello

Following patch removes unused ide0_enable and sata0_enable entries from SB7xx 
and SB600.

Untested.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>


Thanks,
Rudolf
Stefan Reinauer - 2010-08-22 21:39:16
On 8/22/10 10:39 PM, Rudolf Marek wrote:
> Hello
>
> Following patch removes unused ide0_enable and sata0_enable entries
> from SB7xx and SB600.
>
> Untested.
>
> Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Patch

Index: coreboot/src/mainboard/asrock/939a785gmh/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/asrock/939a785gmh/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/asrock/939a785gmh/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -116,10 +116,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48016"
 					register "sphy15_p1" = "0x01b48016"
Index: coreboot/src/southbridge/amd/sb700/chip.h
===================================================================
--- coreboot.orig/src/southbridge/amd/sb700/chip.h	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/southbridge/amd/sb700/chip.h	2010-08-22 12:13:24.000000000 +0200
@@ -22,10 +22,7 @@ 
 
 struct southbridge_amd_sb700_config
 {
-	u32 ide0_enable : 1;
-	u32 sata0_enable : 1;
 	u32 boot_switch_sata_ide : 1;
-	u32 hda_viddid;
 	u32 sphy15_p0;
 	u32 sphy15_p1;
 	u32 sphy15_p2;
Index: coreboot/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/amd/dbm690t/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/amd/dbm690t/devicetree.cb	2010-08-22 12:17:28.000000000 +0200
@@ -106,8 +106,6 @@ 
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # ACI 0x4382
 					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "hda_viddid" = "0x10ec0882"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0
Index: coreboot/src/mainboard/amd/mahogany/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/amd/mahogany/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -106,10 +106,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/mainboard/amd/mahogany_fam10/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany_fam10/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/amd/mahogany_fam10/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -97,10 +97,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/amd/pistachio/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/amd/pistachio/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -68,9 +68,6 @@ 
 				device pci 14.4 on end # PCI 0x4384
 				device pci 14.5 on end # ACI 0x4382
 				device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0
 
Index: coreboot/src/mainboard/amd/tilapia_fam10/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/amd/tilapia_fam10/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/amd/tilapia_fam10/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -98,10 +98,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/mainboard/gigabyte/ma785gmt/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/gigabyte/ma785gmt/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/gigabyte/ma785gmt/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -98,10 +98,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/mainboard/gigabyte/ma78gm/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/gigabyte/ma78gm/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
+++ coreboot/src/mainboard/gigabyte/ma78gm/devicetree.cb	2010-08-22 12:13:24.000000000 +0200
@@ -97,10 +97,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/mainboard/jetway/pa78vm5/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/jetway/pa78vm5/devicetree.cb	2010-08-22 12:13:30.000000000 +0200
+++ coreboot/src/mainboard/jetway/pa78vm5/devicetree.cb	2010-08-22 12:13:45.000000000 +0200
@@ -97,10 +97,7 @@ 
 					end		#LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 2
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-					register "hda_viddid" = "0x10ec0882"
 					# SATA PHY fine tune, depends on PCB layout!
 					register "sphy15_p0" = "0x01b48017"
 					register "sphy15_p1" = "0x01b48019"
Index: coreboot/src/southbridge/amd/sb600/chip.h
===================================================================
--- coreboot.orig/src/southbridge/amd/sb600/chip.h	2010-08-22 12:14:31.000000000 +0200
+++ coreboot/src/southbridge/amd/sb600/chip.h	2010-08-22 12:15:51.000000000 +0200
@@ -22,8 +22,6 @@ 
 
 struct southbridge_amd_sb600_config
 {
-	u32 ide0_enable : 1;
-	u32 sata0_enable : 1;
 	u32 hda_viddid;
 };
 struct chip_operations;
Index: coreboot/src/southbridge/amd/sb600/sb600_ide.c
===================================================================
--- coreboot.orig/src/southbridge/amd/sb600/sb600_ide.c	2010-08-22 12:15:21.000000000 +0200
+++ coreboot/src/southbridge/amd/sb600/sb600_ide.c	2010-08-22 12:15:28.000000000 +0200
@@ -26,11 +26,9 @@ 
 
 static void ide_init(struct device *dev)
 {
-	struct southbridge_amd_sb600_config *conf;
 	/* Enable ide devices so the linux ide driver will work */
 	u32 dword;
 	u8 byte;
-	conf = dev->chip_info;
 
 	/* RPR10.1 disable MSI */
 	dword = pci_read_config32(dev, 0x70);
Index: coreboot/src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/kontron/kt690/devicetree.cb	2010-08-22 12:20:28.000000000 +0200
+++ coreboot/src/mainboard/kontron/kt690/devicetree.cb	2010-08-22 12:20:34.000000000 +0200
@@ -110,8 +110,6 @@ 
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # ACI 0x4382
 					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "hda_viddid" = "0x10ec0888"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0
Index: coreboot/src/mainboard/technexion/tim5690/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/technexion/tim5690/devicetree.cb	2010-08-22 12:19:37.000000000 +0200
+++ coreboot/src/mainboard/technexion/tim5690/devicetree.cb	2010-08-22 12:19:56.000000000 +0200
@@ -106,8 +106,6 @@ 
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # ACI 0x4382
 					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "hda_viddid" = "0x10ec0882"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0
Index: coreboot/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- coreboot.orig/src/mainboard/technexion/tim8690/devicetree.cb	2010-08-22 12:20:03.000000000 +0200
+++ coreboot/src/mainboard/technexion/tim8690/devicetree.cb	2010-08-22 12:20:12.000000000 +0200
@@ -106,8 +106,6 @@ 
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # ACI 0x4382
 					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
 					register "hda_viddid" = "0x10ec0882"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0