Patchwork hardcoded bdf numbers in sb700_early_init.c get serial output on ASUS M4A77TD-PRO

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Submitter xdrudis
Date 2010-08-24 20:43:41
Message ID <20100824204341.GB6151@ideafix.casa.ct>
Download mbox | patch
Permalink /patch/1796/
State New
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Comments

xdrudis - 2010-08-24 20:43:41
Hello. I rewrote my earlier patch to romcc_io.h (where I banned some
device ranges from pci_locate_device) because it was too
aggressive. With this patch to sb700_early_setup.c I achieve the same
on my board (serial output, and it hangs in the same place), but
hopefully with less breakage for other boards. I first tried to hardcode
PCI bus, device and function in sb700_lpc_init() only but it did hang
elsewhere, so I finally thought it more coherent to hardcode all
devices in the file than just some functions, and it works for me. I
still have the doubt of why was there a pci_locate_device in the first
place, since from my more than limited knowledge it does not look like
the devices in sb700 may appear in other bus,device,function
addresses. But the original even had an error message at one place for
when the device was not found.

Please review and/or test and commit if you think appropiate (I guess 
it's not urgent, since my board still does not boot). 

This patch applies to svn 5739 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

---

Thank you for commiting my previous patches. 

Now I plan to have a look at fidvid.c and AMD's Bios and Kernel
Developer Guide. I'm not sure I'll be able to fix much, and it may
take me a while. I guess it's better not to send patches or anything
until I get something that works for me.

Patch

Index: src/southbridge/amd/sb700/sb700_early_setup.c
===================================================================
--- src/southbridge/amd/sb700/sb700_early_setup.c	(revision 5721)
+++ src/southbridge/amd/sb700/sb700_early_setup.c	(working copy)
@@ -49,9 +49,9 @@ 
 
 	/* if (rev != 0) return rev; */
 
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	dev = PCI_DEV(0,0x14,0);
 
-	if (dev == PCI_DEV_INVALID) {
+	if ( pci_read_config32(dev, 0) != PCI_ID(0x1002, 0x4385)) {
 		die("SMBUS controller not found\n");
 		/* NOT REACHED */
 	}
@@ -103,7 +103,8 @@ 
 	u32 reg32;
 	device_t dev;
 
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);	/* SMBUS controller */
+	/* PCI_ID(0x1002, 0x4385) SMBUS controller */
+	dev = PCI_DEV(0,20,0);
 	/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
 	 * This bit has no meaning if debug strap is not enabled. So if the
 	 * board keeps rebooting and the code fails to reach here, we could
@@ -117,7 +118,8 @@ 
 	reg32 |= 1 << 20;
 	pci_write_config32(dev, 0x64, reg32);
 
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	/* PCI_ID(0x1002, 0x439d) LPC Controller */
+	dev = PCI_DEV(0,20,3);
 	/* Decode port 0x3f8-0x3ff (Serial 0) */
 	// XXX Serial port decode on LPC is hardcoded to 0x3f8
 	reg8 = pci_read_config8(dev, 0x44);
@@ -155,11 +157,7 @@ 
 /* what is its usage? */
 static u32 get_sbdn(u32 bus)
 {
-	device_t dev;
-
-	/* Find the device. */
-	dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
-	return (dev >> 15) & 0x1f;
+  return 20; //sb700 SMBUS/ACPI PCI device number 
 }
 
 static u8 dual_core(void)
@@ -236,8 +234,8 @@ 
 	u8 byte;
 	device_t dev;
 
-	/* P2P Bridge */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
+	/* P2P Bridge PCI_ID(0x1002, 0x4384) */
+	dev = PCI_DEV(0,20,4);
 
 	/* Chip Control: Enable subtractive decoding */
 	byte = pci_read_config8(dev, 0x40);
@@ -268,8 +266,8 @@ 
 	byte |= 1 << 0;
 	pci_write_config8(dev, 0x04, byte);
 
-	/* LPC controller */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+	/* LPC controller PCI_ID(0x1002, 0x439D) */
+	dev = PCI_DEV(0,20,3);
 
 	byte = pci_read_config8(dev, 0x4A);
 	byte &= ~(1 << 5);	/* disable lpc port 80 */
@@ -282,14 +280,15 @@ 
 	device_t dev;
 	u32 reg32;
 
-	/* Enable LPC controller */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	/* Enable LPC controller PCI_ID(0x1002, 0x4385) */
+	dev = PCI_DEV(0,20,0);
 	reg32 = pci_read_config32(dev, 0x64);
 	reg32 |= 0x00100000;	/* lpcEnable */
 	pci_write_config32(dev, 0x64, reg32);
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
+	// PCI_ID(0x1002, 0x439d) 
+	dev = PCI_DEV(0,20,3);
 	byte = pci_read_config8(dev, 0x4a);
 	byte |= 1 << 5;		/* enable port 80 */
 	pci_write_config8(dev, 0x4a, byte);
@@ -304,7 +303,8 @@ 
 	printk(BIOS_INFO, "sb700_devices_por_init()\n");
 	/* SMBus Device, BDF:0-20-0 */
 	printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n");
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	//PCI_ID(0x1002, 0x4385)
+	dev = PCI_DEV(0,20,0);
 
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\n");
@@ -380,7 +380,8 @@ 
 
 	/* IDE Device, BDF:0-20-1 */
 	printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
+        dev = PCI_DEV(0,20,1);
 	/* Disable prefetch */
 	byte = pci_read_config8(dev, 0x63);
 	byte |= 0x1;
@@ -388,7 +389,8 @@ 
 
 	/* LPC Device, BDF:0-20-3 */
 	printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+	//PCI_ID(0x1002, 0x439D)
+        dev = PCI_DEV(0,20,3);
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
 
@@ -425,8 +427,9 @@ 
 	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
 	 */
 	printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
-
+	//PCI_ID(0x1002, 0x4384)
+        dev = PCI_DEV(0,20,4);
+	
 	/* Arbiter enable. */
 	pci_write_config8(dev, 0x43, 0xff);
 
@@ -442,7 +445,9 @@ 
 
 	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
 	printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n");
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
+	/* PCI_ID(0x1002, 0x4390) inter alia.
+	   This one changes dev id depending on configuration */
+        dev = PCI_DEV(0,17,0);
 
 	/*PHY Global Control*/
 	pci_write_config16(dev, 0x86, 0x2C00);
@@ -465,7 +470,8 @@ 
 	pmio_write(0x66, byte);
 
 	/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
-	if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) {
+	//PCI_ID(0x1002, 0x4385)
+        if (get_sb700_revision(PCI_DEV(0,20,0)) <= 0x12) {
 		byte = pmio_read(0x65);
 		byte &= ~(1 << 7);
 		pmio_write(0x65, byte);
@@ -527,8 +533,8 @@ 
 	device_t dev;
 	u8 byte;
 
-	/* SMBus Device, BDF:0-20-0 */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	/* SMBus Device, BDF:0-20-0 PCI_ID(0x1002, 0x4385) */
+        dev = PCI_DEV(0,20,0);
 	/* Enable watchdog decode timer */
 	byte = pci_read_config8(dev, 0x41);
 	byte |= (1 << 3);
@@ -540,18 +546,18 @@ 
 	byte |= (1 << 4);
 	pmio_write(0x65, byte);
 
-	/* IDE Device, BDF:0-20-1 */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
+	/* IDE Device, BDF:0-20-1 PCI_ID(0x1002, 0x439C) */
+        dev = PCI_DEV(0,20,1);
 	/* Enable IDE Explicit prefetch, 0x63[0] clear */
 	byte = pci_read_config8(dev, 0x63);
 	byte &= 0xfe;
 	pci_write_config8(dev, 0x63, byte);
 
-	/* LPC Device, BDF:0-20-3 */
+	/* LPC Device, BDF:0-20-3 PCI_ID(0x1002, 0x439D) */
 	/* The code below is ported from old chipset. It is not
 	 * metioned in RPR. But I keep them. The registers and the
 	 * comments are compatible. */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+        dev = PCI_DEV(0,20,3);
 	/* Enabling LPC DMA function. */
 	byte = pci_read_config8(dev, 0x40);
 	byte |= (1 << 2);
@@ -566,12 +572,14 @@ 
 	pci_write_config8(dev, 0x78, byte);
 
 	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
-	dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
+	// PCI_ID(0x1002, 0x4390) . Dev id depends on configuration.
+        dev = PCI_DEV(0,17,0);
 	/* rpr7.12 SATA MSI and D3 Power State Capability. */
 	byte = pci_read_config8(dev, 0x40);
 	byte |= 1 << 0;
 	pci_write_config8(dev, 0x40, byte);
-	if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12)
+	//PCI_ID(0x1002, 0x4385)
+        if (get_sb700_revision(PCI_DEV(0,20,0)) <= 0x12)
 		pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
 	else
 		pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */