Patchwork added ich10r gpio support to intel tool

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Submitter Warren Turkal
Date 2010-08-30 08:39:28
Message ID <AANLkTi=nLgBCaKP=r_txzRQguPU+mjiR0gCcu7FaX1Ut@mail.gmail.com>
Download mbox | patch
Permalink /patch/1813/
State Accepted
Commit r5761
Headers show

Comments

Warren Turkal - 2010-08-30 08:39:28
I have attached a patch for ich10r support for dumping gpio registers.
I am looking for comments and a possible committer.

Thanks,
wt
Paul Menzel - 2010-08-30 10:16:50
Am Montag, den 30.08.2010, 01:39 -0700 schrieb Warren Turkal:
> I have attached a patch for ich10r support for dumping gpio registers.

Thank you for your patch.

> I am looking for comments and a possible committer.

Please take a look at the Development Guideline and especially the
sign-off procedure [1]. Otherwise the developers (not me) cannot commit
your patch.


Thanks,

Paul


[1] http://www.coreboot.org/Development_Guidelines#How_to_contribute

Patch

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 75658a9..9bb23c9 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -152,6 +152,41 @@  static const io_register_t ich9_gpio_registers[] = {
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich10_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "RESERVED" },
+	{ 0x40, 4, "GPIO_USE_SEL3" },
+	{ 0x44, 4, "GPIO_SEL3" },
+	{ 0x48, 4, "GPIO_LVL3" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 4, "RESERVED" },
+	{ 0x54, 4, "RESERVED" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	{ 0x60, 4, "GP_RST_SEL" },
+	{ 0x64, 4, "RESERVED" },
+	{ 0x68, 4, "RESERVED" },
+	{ 0x6c, 4, "RESERVED" },
+	{ 0x70, 4, "RESERVED" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 int print_gpios(struct pci_dev *sb)
 {
 	int i, size;
@@ -161,6 +196,11 @@  int print_gpios(struct pci_dev *sb)
 	printf("\n============= GPIOS =============\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_ICH10R:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich10_gpio_registers;
+		size = ARRAY_SIZE(ich10_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH9DH:
 	case PCI_DEVICE_ID_INTEL_ICH9DO:
 	case PCI_DEVICE_ID_INTEL_ICH9R: