Patchwork Alix.2D3 / Coreboot v4 support

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Submitter Aurélien
Date 2010-08-30 18:29:50
Message ID <AANLkTimxt+i-CBqhSQtro+Rk7Tg+p=pJ8M1DS3Zz=vpw@mail.gmail.com>
Download mbox | patch
Permalink /patch/1820/
State Superseded
Headers show

Comments

Aurélien - 2010-08-30 18:29:50
On Wed, Aug 25, 2010 at 5:27 PM, Patrick Georgi <patrick@georgi-clan.de>wrote:

> > Loading stage image.
> > Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @
> > 0x100000
> > lzma: Decoding error = 1
> > CBFS: LZMA decompression failed!
> > Loading stage failed!
> > --- hangs here ---
> This is the first time that RAM beyond 1MB is seriously used. On other
> Geode boards, some MSRs weren't set up early enough, so >1MB wasn't
> reachable. http://patchwork.coreboot.org/patch/1485/ provides a partial
> fix, but I suspect that the LX code has similar issues.
>
>
In fact, I just realized that this patch works just fine on my board (though
this code has been moved to src/cpu/model_lx, which confused me.

~~~
Loading stage image.
Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @
0x100000
Stage: done loading.
Jumping to image.
~~~

So, here's the patch. I suppose the RAM may be incorrectly setup initially
(size...), but it is re-setup just after by the northbridge init code, so I
think it's just fine.

Also, who's responsible for updating the wiki ? Since this is a newly
supported board, I think it should appear in v4 support list. I gave the
details in a previous post. I can update it myself, but I'll need an
account, and I don't think it's really worth the trouble, just for one
board.

Signed-off-by: Aurélien Guillaume <aurelien@iwi.me>

Thanks :)

Patch

Index: src/cpu/amd/model_lx/msrinit.c
===================================================================
--- src/cpu/amd/model_lx/msrinit.c	(revision 5755)
+++ src/cpu/amd/model_lx/msrinit.c	(working copy)
@@ -33,12 +33,15 @@ 
 	{CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
 
 	/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
+	/* Also pre-setup memory above 1MB, to allow for RAMBASE=1000000. */
 	{MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
 	{MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
 	{MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+	{MSR_GLIU0_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
 	{MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
 	{MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
 	{MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+	{MSR_GLIU1_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
 };
 
 static void msr_init(void)
Index: src/mainboard/pcengines/alix2d3/Kconfig
===================================================================
--- src/mainboard/pcengines/alix2d3/Kconfig	(revision 5755)
+++ src/mainboard/pcengines/alix2d3/Kconfig	(working copy)
@@ -24,8 +24,4 @@ 
 	int
 	default 6
 
-config RAMBASE
-	hex
-	default 0x4000
-
 endif # BOARD_PCENGINES_ALIX2D3